A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

In a first sensitivity level, an AD converter performs AD conversion selectively using, in accordance with the level of the analog signal, any one of a first reference signal and a second reference signal that have mutually different slopes, and in a second sensitivity level that is different from the first sensitivity level, the AD converter performs AD conversion only using a third reference signal.

The present disclosure relates to a comparator, an AD converter, a solid-state image pickup device, an electronic device, a method of controlling the comparator, a data writing circuit, a data reading circuit, and a data transferring circuit, capable of improving the determining speed of the comparator and reducing power consumption. The comparator includes: a differential input circuit configured to operate with a first power supply voltage, the differential input circuit configured to output a signal when an input signal is higher than a reference signal in voltage; a positive feedback circuit configured to operate with a second power supply voltage lower than the first power supply voltage, the positive feedback circuit being configured to accelerate transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, on the basis of the output signal of the differential input circuit; and a voltage conversion circuit configured to convert the output signal of the differential input circuit into a signal corresponding to the second power supply voltage. The present disclosure can be applied to, for example, a comparator of a solid-state image pickup device.

Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.

An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

A photodetection device according to the present disclosure includes: a pixel; a reference signal generation unit; a comparison circuit; and a first switch. The pixel is configured to generate a pixel signal. The reference signal generation unit is configured to generate a reference signal. The comparison circuit includes a first-stage amplifier circuit and a second-stage amplifier circuit that is coupled to the first-stage amplifier circuit through a connection node. The first-stage amplifier circuit is configured to output a first output signal corresponding to a comparison operation based on the pixel signal and the reference signal. The second-stage amplifier circuit is configured to output a second output signal corresponding to the first output signal outputted from the first-stage amplifier circuit through the connection node. The first switch has one end and another end. The one end is coupled to the connection node. The first switch allows impedance and a voltage at the connection node to change.

An imaging system according to the present disclosure includes: an imaging device that is mounted in a vehicle, and captures and generates an image of a peripheral region of the vehicle; and a processing device that is mounted in the vehicle, and executes processing related to a function of controlling the vehicle on the basis of the image. The imaging device includes: a first control line, a first voltage generator that applies a first voltage to the first control line, a first signal line, a plurality of pixels that applies a pixel voltage to the first signal line, a first dummy pixel that applies a voltage corresponding to the first voltage of the first control line to the first signal line in a first period, a converter including a first converter that performs AD conversion on the basis of a voltage of the first signal line in the first period to generate a first digital code, and a diagnosis section that performs diagnosis processing on the basis of the first digital code. The above-described processing device restricts the function of controlling the vehicle on the basis of a result of the diagnosis processing.

An image sensor for sampling a pixel signal a plurality of times during a readout time includes an analog comparator configured to compare a signal level of the pixel signal with a signal level of a target ramp signal that is any one of a plurality of ramp signals, a counter configured to output counting data based on a comparison result of the analog comparator, and a digital comparing circuit configured to compare a binary value of a target reference code corresponding to the target ramp signal with a binary value of the counting data and determine whether to output a digital signal corresponding to the counting data to a data output circuit based on a result of the comparison between the binary value of the counting data and the binary value of the target reference code.

There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.

An optical light sensing device includes a detector operable to detect a light wave. The optical light sensing device also includes an integration circuit that includes an operational amplifier that is operable to reduce or cancel dark currents generated at the detector.