An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

A technique for generating analog waveforms includes combining a desired, in-band signal with a randomizing, out-of-band signal at an input of a DAC, operating the DAC to generate DAC output based on a combination of the desired signal and the randomizing signal, and filtering the DAC output to pass the desired signal while removing the randomizing signal.

A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.

A light detection and ranging (lidar) receiver may include a first photodiode, a first amplifier connected to the first photodiode, and a first analog-to-digital converter (ADC) connected to an output of the first amplifier. The lidar receiver may include a second photodiode, a second amplifier connected to the second photodiode, and a second ADC connected to the second amplifier. The lidar may include a processor connected to an output of the first ADC and an output of the second ADC and a direct-current-to-direct-current converter connected to an output of the processor and to the first photodiode and the second photodiode. The processor may determine, based on the output of the first ADC and the output of the second ADC, a first bias to apply to the first photodiode and a second bias to apply to the second photodiode.

A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

A light detection and ranging (lidar) receiver may include a first photodiode, a first amplifier connected to the first photodiode, and a first analog-to-digital converter (ADC) connected to an output of the first amplifier. The lidar receiver may include a second photodiode, a second amplifier connected to the second photodiode, and a second ADC connected to the second amplifier. The lidar may include a processor connected to an output of the first ADC and an output of the second ADC and a direct-current-to-direct-current converter connected to an output of the processor and to the first photodiode and the second photodiode. The processor may determine, based on the output of the first ADC and the output of the second ADC, a first bias to apply to the first photodiode and a second bias to apply to the second photodiode.

The present disclosure provides an analog-to-digital converter system comprising a sampler configured to sample an input signal and provide at least two output signals with a predetermined output sample rate, and an analog-to-digital converter for each one of the output signals and configured to convert the respective output signal into a digital signal with a predetermined converter sample rate, wherein the converter sample rate is higher than the output sample rate. Further, the present disclosure provides a respective method.

An integrated circuit may include a ranging receiver that includes an analog-to-digital converter (ADC) having a time-variant sampling or data rate. Notably, the sampling rate may be increased when a return signal is detected by the ranging receiver. For example, the return signal may be detected using a matched filter (such as a correlation of the return signal and a target signal) and a comparator having a time-variant threshold. The time-variant threshold may be decreased as a function of time after a transmit signal is output in order to track the channel response, such as a decrease in the return signal amplitude for objects at larger ranges. Alternatively or additionally, the sampling rate may be increased based at least in part on a predefined function (such as a closed-form expression or a stepwise function, e.g., a stairstep function) after the transmit signal is output.

A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.

An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC to a second digital conversion output from the ADC.