An analog-to-digital conversion apparatus is provided. The analog-to-digital conversion apparatus includes an integrated circuit (IC) configured to generate a first interrupt request; and an analog-to-digital converter included in an integrated circuit, wherein the analog-to-digital converter is configured to receive a plurality of analog values from a plurality of channels, and convert at least a portion of the received analog values that correspond to at least a portion of channels of the plurality of channels, that are selected based on the first interrupt request into at least a portion of digital values.

A method for differentiator-based compression of digital data includes (a) multiplying a tap-weight vector by an original data vector to generate a predicted signal, the original data vector comprising N sequential samples of an original signal, N being an integer greater than or equal to one, (b) using a subtraction module, subtracting the predicted signal from a sample of the original signal to obtain an error signal, (c) using a quantization module, quantizing the error signal to obtain a quantized error signal, and (d) updating the tap-weight vector according to changing statistical properties of the original signal.

An analog-to-digital converting device configured to convert an analog signal into a digital signal, including a meta-stability detection unit configured to output a meta-stability signal based on a comparison result, wherein the comparison result is determined by comparing a comparison voltage of each bit of the digital signal with the analog signal; a counter configured to count a number of times that the comparison voltage of each bit of the digital signal is compared with the analog signal; and a control logic configured to detect a bit at which meta-stability has occurred from among bits of the digital signal based on the meta-stability signal and the counted number.

Circuit and method for encoding an analog signal to a stream of bits at an Analog to Digital Converter (ADC) and subsequent reconstruction of the original signal from the bit stream at a Digital to Analog Converter (DAC), where the ADC module samples the analog signal at a sub-Nyquist rate and encodes the samples to a stream of bits. The bit steam is subsequently used to reconstruct the Nyquist-rate samples of the original analog signal at the DAC. The ADC samples the input signal in one of the two realizations of non-uniform sampling, namely, Random Sampling (RS) and Level Crossing (LC) sampling techniques, according to embodiments of the disclosed invention.

In order to provide a highly precise analog/digital conversion system in which an output error of an AD converter is small, sampling is performed at a certain sampling period S from the start time of a measurement period TL to the (N−1)-th sampling when the measurement period TL does not correspond to the sampling period S multiplied by the number of samplings N, the N-th sampling is performed at a timing when a time interval between the (N−1)-th sampling and the N-th sampling is equal to the sampling period S multiplied by a predetermined coefficient k, and the k value is set to a non-integer optimum value evaluated in advance in accordance with the N value in order to minimize an error of the detection value of the AD converter.

A novel and useful digitally intensive event-driven quasi-level crossing (quasi-LC) delta modulator analog to digital converter (ADC) with adaptive resolution (AR) for Internet of Things (IoT) wireless networks. Minimizing the average sampling rate for sparse input signals significantly reduces the power consumed in data transmission, processing, and storage. The AR quasi-LC delta modulator quantizes the residue voltage signal with a 4-bit asynchronous successive approximation register (SAR) sub-ADC, which enables a straightforward implementation of LC and AR algorithms in the digital domain. The modulator achieves data compression by means of a globally signal dependent average sampling rate and achieves AR through a digital multilevel comparison window that overcomes the tradeoff between the dynamic range and the input bandwidth in conventional LC ADCs. Engaging the AR algorithm reduces the average sampling rate by a factor of three at the edge of the modulator's signal bandwidth.

A method and system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver. The transceiver includes a transmit path, a receive path, and an observation path. The observation path includes an analog buffer and an observation ADC. A controller generates a control signal to control sampling events at the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants. The controller may also generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not. The digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid. The digital data indicated as invalid may be discarded and the digital data indicated as valid is used for calibration of the transmit path or the receive path.

An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a comparison circuit, a control circuit, a digital-to-analog (D/A) conversion circuit, a switched buffer and a loop filter. The track-and-hold circuit is configured to output a first signal based on an input signal or a first timing signal. The comparison circuit is configured to generate a comparison result based on the first signal and a filtered residue signal. The control circuit is coupled to the comparison circuit, and is configured to generate an N-bit logical signal according to N comparison results from the comparison circuit. The D/A circuit is configured to generate a feedback signal based on the N-bit logical signal. The switched buffer is configured to generate a first error signal based on a second timing signal and a second error signal. The loop filter is configured to generate the filtered residue signal based on the first error signal.

A sample and hold readout system and method for ramp analog to digital conversion is presented in which an optical array is read out using a sample and hold circuit such that each sample is used to charge a sample and hold capacitor and is read out during a hold phase using an amplifier that drives an ramp analog to digital converter. The sample and hold circuit transitions to a tracking phase wherein the optical array input drives an amplifier that drives the sample and hold capacitor then transitions to a sample phase where the sample and hold capacitor is connected to the optical array output directly.

An analog-to-digital conversion apparatus is provided. The analog-to-digital conversion apparatus includes an integrated circuit (IC) configured to generate a first interrupt request; and an analog-to-digital converter included in an integrated circuit, wherein the analog-to-digital converter is configured to receive a plurality of analog values from a plurality of channels, and convert at least a portion of the received analog values that correspond to at least a portion of channels of the plurality of channels, that are selected based on the first interrupt request into at least a portion of digital values.