Patent classifications
H03M1/1285
High bandwidth under-sampled successive approximation register analog to digital converter with nonlinearity minimization
Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.
Spur reduction for analog-to-digital converters
Methods, systems, computer-readable media, and apparatuses for spurious information reduction in a data signal are presented. One example of such an apparatus includes a data converter including a plurality of analog-to-digital converters (ADCs) and configured to produce a plurality of sampled signals, a normalizer configured to obtain a plurality of common-bandwidth signals from at least the plurality of sampled signals, and a common-mode filter configured to produce a digital output signal based on the plurality of common-bandwidth signals.
Multiple sinusoid signal sub-Nyquist sampling method based on multi-channel time delay sampling system
The disclosure discloses a multiple sinusoid signal sub-Nyquist sampling method based on a multi-channel time delay sampling system. The method includes step 1: initializing; step 2: enabling multiple sinusoid signals x(t) to respectively enter N′ parallel sampling channels after the multiple sinusoid signals are divided, wherein a sampling time delay of adjacent channels is τ, and the number of sampling points of each channel is N; step 3: combining sampled data of each sampling channel to construct an autocorrelation matrix R.sub.xx, and estimating sampling signal parameters c.sub.m of each channel and a set of frequency parameters {circumflex over (f)}.sub.m by utilizing the ESPRIT method; step 4: estimating signal amplitudes α.sub.m and another set of frequency parameters
HIGH BANDWIDTH UNDER-SAMPLED SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER WITH NONLINEARITY MINIMIZATION
Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.
SPUR REDUCTION FOR ANALOG-TO-DIGITAL CONVERTERS
Methods, systems, computer-readable media, and apparatuses for spurious information reduction in a data signal are presented. One example of such an apparatus includes a data converter including a plurality of analog-to-digital converters (ADCs) and configured to produce a plurality of sampled signals, a normalizer configured to obtain a plurality of common-bandwidth signals from at least the plurality of sampled signals, and a common-mode filter configured to produce a digital output signal based on the plurality of common-bandwidth signals.
Quantum processing apparatus with downsampling analog-to-digital converter
Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M>1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the n.sup.th Nyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the n.sup.th Nyquist zone to the m.sup.th Nyquist zone of the spectrum, where n>m≥1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.
Multiple Sinusoid Signal Sub-Nyquist Sampling Method Based on Multi-channel Time Delay Sampling System
The disclosure discloses a multiple sinusoid signal sub-Nyquist sampling method based on a multi-channel time delay sampling system. The method includes step 1: initializing; step 2: enabling multiple sinusoid signals x(t) to respectively enter N′ parallel sampling channels after the multiple sinusoid signals are divided, wherein a sampling time delay of adjacent channels is τ, and the number of sampling points of each channel is N; step 3: combining sampled data of each sampling channel to construct an autocorrelation matrix R.sub.xx, and estimating sampling signal parameters c.sub.m of each channel and a set of frequency parameters {circumflex over (f)}.sub.m by utilizing the ESPRIT method; step 4: estimating signal amplitudes α.sub.m and another set of frequency parameters
QUANTUM PROCESSING APPARATUS WITH DOWNSAMPLING ANALOG-TO-DIGITAL CONVERTER
Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M>1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the n.sup.th Nyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the n.sup.th Nyquist zone to the m.sup.th Nyquist zone of the spectrum, where n>m≥1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.
High bandwidth under-sampled successive approximation register analog to digital converter with nonlinearity minimization
Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.
Ad converting device and electronic apparatus
A wireless communication device converts a signal component, which has one of distributed frequency bands in an analog RF signal and passes through one of a plurality of bandpass filters, into digital data with an AD converter that carries out undersampling. A sampling frequency of the AD converter is set so that frequencies which are integral multiples of a Nyquist frequency based on the sampling frequency do not fall within frequency bands of signal components which are of the RF signal and are to pass through the respective plurality of bandpass filters.