Patent classifications
H03M1/142
RETENTION DRIFT CORRECTION IN NON-VOLATILE MEMORY ARRAYS
Methods and architectures for refreshing memory elements in a memory array may initialize a reference array that stores each of the possible values stored in the memory element. The values in the memory array and the reference array will drift in parallel over time. To perform a refresh, the drifted values may be read from the reference array and mapped to the original values that were stored when the reference array was initialized. Next, each value may be read from the memory array and matched with a corresponding value from the reference array. The known original value stored in the reference array can then be used to refresh the corresponding memory element in the memory array.
Retention drift correction in non-volatile memory arrays
Methods and architectures for refreshing memory elements in a memory array may initialize a reference array that stores each of the possible values stored in the memory element. The values in the memory array and the reference array will drift in parallel over time. To perform a refresh, the drifted values may be read from the reference array and mapped to the original values that were stored when the reference array was initialized. Next, each value may be read from the memory array and matched with a corresponding value from the reference array. The known original value stored in the reference array can then be used to refresh the corresponding memory element in the memory array.
CALIBRATION OF ELECTRICAL PARAMETERS IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network. In one example, a system comprises a digital-to-analog converter for receiving an input of k bits and generating a first analog output, a mapping scalar for converting the first analog output into a second analog output, and an analog-to-digital converter for generating an output of n bits from the second analog output, where n is a different value than k.
Semiconductor device and AD conversion device
A semiconductor device includes an AD conversion unit that performs AD conversion on an input signal based on a reference voltage to be supplied, a reference voltage detection unit that detects the reference voltage supplied to the AD conversion unit, and a control unit that corrects a result of the AD conversion by the AD conversion unit in accordance with the reference voltage detected by the reference voltage detection unit. Thereby, AD conversion can be performed accurately even when a reference voltage varies.
SEMICONDUCTOR DEVICE AND AD CONVERSION DEVICE
A semiconductor device includes an AD conversion unit that performs AD conversion on an input signal based on a reference voltage to be supplied, a reference voltage detection unit that detects the reference voltage supplied to the AD conversion unit, and a control unit that corrects a result of the AD conversion by the AD conversion unit in accordance with the reference voltage detected by the reference voltage detection unit. Thereby, AD conversion can be performed accurately even when a reference voltage varies.
Systems and methods for implementing a feedback-informed memory programming of an integrated circuit
A method is disclosed for programming analog-valued weights in a non-volatile memory array using feedback-based estimation and adaptive pulse modulation. The method includes initializing a target weight, applying one or more programming pulses to a memory cell, estimating a weight state of the memory cell based on analog-to-digital conversion, determining a residual error between the estimated weight state and the target weight, and computing a subsequent programming pulse based on the residual error. The subsequent pulse may be adjusted by selecting a programming voltage from a quantized set of levels responsive to the recent weight response dynamics. The programming process may iterate until convergence may be achieved within a defined threshold. The technique supports precise control of conductance programming using closed-loop feedback and may be compatible with pulse-width, amplitude, and polarity modulation schemes.