Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

A dynamic high-resolution ADC according to an example embodiment may include a dynamic amplifier configured to amplify, by as much as a first gain, the sampled-and-held analog signal received from the sample and hold circuit; DAC configured to convert a digital signal input from a decoder into an analog signal; a residue signal amplifier connected to the dynamic amplifier and the DAC and configured to calculate a difference between an output signal of the dynamic amplifier and an output signal of the DAC and amplify the difference by as much as a second gain; an ADC connected to the residue signal amplifier and configured to convert an output signal of the residue signal amplifier into a digital signal; and a decoder connected to the ADC and configured to decode, into digital data, an output signal of the ADC input by the ADC.

An image sensor includes a pixel sensor outputting an analog sampling signal; a sampling unit comparing the sampling signal and a ramp signal, and outputting a comparison signal that is time-axis length information; and a counter counting a length of the comparison signal based on a clock signal and first and second complement control signals. The counter includes an AND gate ANDing the comparison signal and the clock signal; and a counting unit triggered at a falling edge of the AND gate output to output a count value. The counting unit includes a complement operation controller storing an inverted count value that is an inversion of the count value in response to the first complement control signal, and outputting the inverted count value in response to the second complement control signal; and a D-flip-flop that is set or reset depending on the inverted count value, and outputs the count value.

Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

An analog-to-digital converter configured to convert an analog signal into a digital signal includes a first converter configured to receive an input signal of an analog type, compare the input signal with a plurality of reference signals, select one of the plurality of reference signals based on the comparison, and output an upper bit that is a portion of the digital signal based on the selected reference signal, a second converter configured to perform an oversampling operation n times based on a residue signal indicating a difference between an upper analog signal corresponding to the upper bit value and the input signal and output an intermediate bit value of the digital signal corresponding to the first to n-th oversampling signals generated respectively during the oversampling operations performed n times, and a third converter configured to output a lower bit value of the digital signal corresponding to the n-th oversampling signal.

According to the present disclosure, column circuits operate selectively in a first drive mode to output a comparison signal or a second drive mode to acquire a correction value of a first reference signal and a second reference signal, and a selector circuit of a second column circuit selects the same reference signal out of the first reference signal and the second reference signal in the first drive mode and the second drive mode.

Apparatuses and techniques are described for providing a positive voltage source and a negative voltage source in a circuit. The positive voltage source and the negative voltage source have a common ground node. The positive voltage source can be provided using a current mirror in which a current in a first path is copied to provide a current in a second path. The currents of the first and second paths are sunk at the common ground node. The negative voltage source can be provided using a current mirror in which a current in a third path is copied to provide a current in a fourth path, where the current of the fourth path is sourced at the common ground node.

An image sensor includes a pixel sensor outputting an analog sampling signal; a sampling unit comparing the sampling signal and a ramp signal, and outputting a comparison signal that is time-axis length information; and a counter counting a length of the comparison signal based on a clock signal and first and second complement control signals. The counter includes an AND gate ANDing the comparison signal and the clock signal; and a counting unit triggered at a falling edge of the AND gate output to output a count value. The counting unit includes a complement operation controller storing an inverted count value that is an inversion of the count value in response to the first complement control signal, and outputting the inverted count value in response to the second complement control signal; and a D-flip-flop that is set or reset depending on the inverted count value, and outputs the count value.

A readout circuit that includes an amplifier circuitry, an analog-to-digital converter, a feedback circuit and a control logic is introduced. The amplifier circuitry may receive and amplify a differential signal that is obtained according to an input signal and a feedback signal to generate an amplified signal. The analog-to-digital converter is configured to convert the amplified signal to generate a n-bit digital code, wherein n is a positive integer. The feedback circuit is configured to search and generate a m-bit digital code based on a value of the n-bit digital code and convert the m-bit digital code to generate the feedback signal, wherein m is a positive integer. The control logic is coupled to the analog-to-digital converter and the feedback circuit, and configured to control the analog-to-digital converter and the feedback circuit. A multi-bit digital output of the readout circuit is generated according to the n-bit digital code and the m-bit digital code.

According to the present disclosure, column circuits operate selectively in a first drive mode to output a comparison signal or a second drive mode to acquire a correction value of a first reference signal and a second reference signal, and a selector circuit of a second column circuit selects the same reference signal out of the first reference signal and the second reference signal in the first drive mode and the second drive mode.