A switched-capacitor amplifier comprises a comparator, sample and amplification capacitors and a controller to control charge and discharge current sources in dependence on an output signal of the comparator. A closed loop control circuit is configured to determine the delay of the comparator and control an offset of the comparator in response to the determined delay.

An analog-to-digital converter comprising a plurality of sampling cells. At least one of the plurality of sampling cells comprises a capacitive element coupled to a cell output of the at least one of the plurality of sampling cells, wherein a cell output signal is provided at the cell output. The at least one of the plurality of sampling cells further comprises a first cell input for receiving an input signal to be digitized, and a second cell input for receiving a calibration signal. Additionally, the at least one of the plurality of sampling cells comprises a first switch circuit capable of selectively coupling the first cell input to the capacitive element based on a clock signal, and a second switch circuit capable of selectively coupling the second cell input to the capacitive element, wherein a size of the second switch circuit is smaller than a size of the first switch circuit.

A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.

An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.

The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.

A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.

A photoelectric conversion device includes a plurality of pixels configured to output analog voltage signals in response to incident light; an analog memory configured to store the analog voltage signals output from the plurality of pixels; and an analog/digital (A/D) converter configured to perform A/D conversion on the analog voltage signal from the analog memory. The plurality of pixels includes N pixels configured to simultaneously output analog voltage signals to the analog memory. The A/D converter includes (N−1) or less A/D converters configured to perform A/D conversion on the analog voltage signals that have been simultaneously output from the N pixels and stored in the analog memory.

Uniformly-sampled, residue-generating analog-to-digital converters (ADCs), such as uniformly-sampled continuous-time pipelined ADCs, suffer from over-ranging of the residue signal, which can lead to severe signal distortion. Conventionally, power consuming techniques and oversampling are used to address the over-ranging problem. To reduce the range of the residue signal and reduce other impairments, an event-driven sub-quantizer (sub-ADC) and a sub-digital-to-analog converter (sub-DAC) can be implemented in at least one of the stages of the residue-generating ADC, to generate a continuous-time residue signal.

An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.

A multiplying digital-to-analog converter (MDAC) includes an operational amplifier, a sampling capacitor circuit, a pre-sampling capacitor circuit, and a switch circuit. During a sampling cycle, the switch circuit connects a pre-defined voltage and reference voltages to the pre-sampling capacitor circuit, disconnects the pre-sampling capacitor circuit from an input port of the operational amplifier and the sampling capacitor circuit, disconnects an output port of the operational amplifier from the sampling capacitor circuit, and connects a voltage input to the sampling capacitor circuit. During a conversion cycle, the switch circuit connects the pre-sampling capacitor circuit to the sampling capacitor circuit, disconnects the pre-defined voltage and the reference voltages from the pre-sampling capacitor circuit, connects the pre-sampling capacitor circuit to the input port of the operational amplifier, connects the output port of the operational amplifier to the sampling capacitor circuit, and disconnects the voltage input from the sampling capacitor circuit.