Disclosed are a hybrid mode based audio processing method and an apparatus therefor. A hybrid mode based audio processing apparatus according to an exemplary embodiment of the present disclosure includes a signal converting unit which converts a digital signal of an input sound source into an analog signal; a mode controller which analyzes the input sound source, sets an amplification mode according to the analysis result, and generates an amplification control signal to control the amplification mode; an amplifying unit which amplifies the analog signal in the amplification mode set based on the amplification control signal; and an audio output unit which outputs an audio corresponding to the amplified analog signal.

A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).

A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.

Systems and methods are provided for a pipelined analog-to-digital converter (ADC) circuit. The pipelined ADC circuit comprises a plurality of stages. Each stage comprises a differential input configured to receive a differential signal, a multiplying digital-to-analog converter (MDAC) electrically coupled to the input configured to stack voltages of a set of capacitors; a comparator electrically disposed after the MDAC to compare the differential voltages; and a source follower buffer electrically coupled to the first signal line and the second signal line and electrically disposed after the comparator, wherein the MDAC is configured to amplify an output voltage using passive multiplication; and an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages, wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal.

A time-to-digital converter utilizes both coarse and fine quantizers and addresses mismatch by using redundant bits in the coarse time representation and the fine time representation. The redundant bits are compared and if the redundant bits are the same, no mismatch correction is required but if the redundant bits are different a correction is applied to correct the redundant portion of the coarse time information. The redundant portion includes the most significant bit generated by the fine quantizer and the least significant bit of the coarse quantizer. The correction adds to or subtracts from the redundant information.

A time-to-digital converter utilizes both coarse and fine quantizers and addresses mismatch by using redundant bits in the coarse time representation and the fine time representation. The redundant bits are compared and if the redundant bits are the same, no mismatch correction is required but if the redundant bits are different a correction is applied to correct the redundant portion of the coarse time information. The redundant portion includes the most significant bit generated by the fine quantizer and the least significant bit of the coarse quantizer. The correction adds to or subtracts from the redundant information.

A pipelined ADC that does not wait for the residue of a signal to settle to be delivered to the next stage of the pipeline, and thus passes signals to subsequent stages at faster than conventional speeds. A pipelined ADC is used that processes signals representing the boundaries of the search space. Thus, each stage does not necessarily receive the signal as pre-processed by the prior stage, but rather the search space boundaries as pre-processed by the prior stage. Reducing the “search space” of the ADC is equivalent to creating the residues in each step of a pipeline as in the prior art. An ADC operating in this fashion operates without error even if the residual search space boundary outputs from one state are presented to the next stage before the outputs have settled, and can run faster for a given power and bandwidth.

A circuit and a calibrating method are provided. A pixel sensor senses a terminal voltage of a driving transistor during a sensing period. A calibration sensor senses a first predetermined voltage and a second predetermined voltage during a calibration period. An amplifying circuit amplifies the terminal voltage according to a gain, and amplifies the first predetermined voltage and the second predetermined voltage according to the gain. An analog to digital converter converts the amplified terminal voltage into a digital code, and converts the amplified first predetermined voltage into a first digital code and converts the amplified second predetermined voltage into a second digital code. A gain adjusting circuit adjusts the gain according to the first digital code and the second digital code. Accordingly, the gain of the amplifying circuit is calibrated.

The present invention provides a comparator circuit applicable to a high-speed pipeline ADC. The comparator circuit includes a switch capacitor circuit, a pre-amplification circuit, and a latch circuit. The pre-amplification circuit includes a pre-amplifier, a resistance-adjustable device, two switches. The latch circuit includes a differential static latch, a first capacitor, a second capacitor, and a third switch. The transmission rates of a sampling phase and a setup phase can be increased.