An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2.sup.(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2.sup.(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a discrete set of analog dither offset voltages, wherein at least two of the discrete set of analog dither offset voltages are different from each other, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein the waveform has a waveform duration, generate a timing alignment to align each waveform of the analog repetitive signal and the corresponding analog dither offset voltage over the waveform duration, combining, based on the timing alignment, each waveform and the corresponding analog dither offset voltage over the waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal.

Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a time-varying dither signal, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein each waveform has a waveform duration, wherein an average of the time-varying dither signal over multiple waveform durations is substantially zero, and wherein the time-varying dither signal varies over each waveform duration, generating a timing alignment, combining each waveform with the corresponding portion of the time-varying dither signal over each waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal, wherein the timing alignment is used to align the multiple instances of the waveform in the analog output signal.

A device for digitizing an analogue signal, wherein a distortion signal outlet of a distortion signal generator is only coupled to an analogue digital converter by passive components.

The present invention provides a signal processor that improves a resolution of a phase detection without increasing a clock frequency of a controller or decreasing a frequency of an excitation signal. A signal processor 10 includes a comparator 11 that compares a signal obtained by phase modulating a carrier frequency at a rotor rotation angle of a resolver with a dither signal.

A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

A capacitive sensing system operates according to a method which uses an ADC. The analog signal to be digitized is modulated with a triangular or saw-tooth modulating signal, so that a modulated analog signal is obtained, which is sampled with the ADC. The triangular or saw-tooth signal is chosen to have a peak-to-peak amplitude corresponding at least approximately to an integer multiple L, with L≥1, of the quantization step size of the ADC. The saw-tooth or triangular signal has a number M, of periods per each sequence of N samples. M and N are chosen such that M>1 and M≠N and such that R=r*N/(k*gcd(N, M)*L), where gcd(M, N) is the greatest common divisor of N and M and where k=2 if the modulating signal is a saw-tooth signal and k=4 if the modulating signal is a triangular signal.

A circuit device includes a clock generation circuit, a signal generation circuit, a phase comparison circuit, and a processing circuit. The signal generation circuit generates a first signal making the transition at a transition timing of a first clock signal, a fine-judging signal making the transition at a transition timing of a second clock signal, a first coarse-judging signal making the transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making the transition at a transition timing of the second clock signal posterior to the fine-judging signal. The phase comparison circuit performs the phase comparison between the second signal making the transition based on the first signal and each of the fine-judging signal, the first coarse-judging signal, and the second coarse-judging signal. The processing circuit sets the transition timing of the first signal and the transition timing of the fine-judging signal based on the phase comparison result, and converts a time difference between the first signal and the second signal into a digital value based on the setting result.

An image sensor may contain an array of imaging pixels. Each pixel column outputs signals that are read out using a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include at least first and second input sampling capacitors, a comparator, a capacitive digital-to-analog converter (CDAC), and associated control circuitry. If desired, the SAR ADC may include a bank of more than two input sampling capacitors alternating between sampling and conversion. The first capacitor may be used to sample an input signal while conversion for the second capacitor is taking place. Prior to conversion, an input voltage of the comparator and an output voltage of the CDAC may be initialized. During conversion of the signal on the first capacitor, the first capacitor is embedded within the SAR ADC feedback loop to prevent charge sharing between the input sampling capacitor and the CDAC, thereby mitigating potential capacitor mismatch issues.

Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a time-varying dither signal, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein each waveform has a waveform duration, wherein an average of the time-varying dither signal over multiple waveform durations is substantially zero, and wherein the time-varying dither signal varies over each waveform duration, generating a timing alignment, combining each waveform with the corresponding portion of the time-varying dither signal over each waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal, wherein the timing alignment is used to align the multiple instances of the waveform in the analog output signal.