An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2.sup.K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2.sup.L reference times corresponding to 2.sup.L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.

An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2.sup.K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2.sup.L reference times corresponding to 2.sup.L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.

An optical encoder includes an encoding disk and an optical detector disposed to correspond to the encoding disk. The optical detector includes a plurality of optical sensors arranged to form an optical sensor array. The optical detector is provided to receive light. The optical detector includes at least one optical sensor arranged to form at least one sensor array. The width of the sensor array corresponds to an interpolation period of the optical encoder.

An optical encoder includes an encoding disk and an optical detector disposed to correspond to the encoding disk. The optical detector includes a plurality of optical sensors arranged to form an optical sensor array. The optical detector is provided to receive light. The optical detector includes at least one optical sensor arranged to form at least one sensor array. The width of the sensor array corresponds to an interpolation period of the optical encoder.

In a distance measurement apparatus, a light emitter emits pulse-like light. A light receiver receives reflected light of the emitted light and converts the received light to an electrical signal. An AD converter converts the electrical signal to a digital value at a predetermined sampling rate to generate a conversion data series. An interpolation processor upsamples the outputted conversion data series by inserting interpolation data therein to generate an up-data series. A distance calculator calculates a distance to an object that reflects light using a signal waveform indicated by the up-data series. The interpolation processor inserts the interpolation data having an interpolation value between pieces of data belonging to the conversion data series, and smooths the data series in which the interpolation data is inserted using a low-pass filter that has characteristics in which waveform distortion caused by ringing does not occur.

A SAR ADC includes a first capacitor array, a first comparator, a second capacitor array, a second comparator, an arbiter and a control circuit. The first capacitor array is arranged for receiving an input signal to generate a first signal. The first comparator is arranged for comparing the first signal with a first reference signal to generate a first comparison result. The second capacitor array is arranged for receiving the input signal to generate a second signal. The second comparator is arranged for comparing the second signal with a second reference signal to generate a second comparison result. The arbiter is arranged for generating an arbitration result according to the first comparison result and the second comparison result. The control circuit is arranged for generating an output signal according to the first comparison result, the second comparison result and the arbitration result.

In a distance measurement apparatus, a light emitter emits pulse-like light. A light receiver receives reflected light of the emitted light and converts the received light to an electrical signal. An AD converter converts the electrical signal to a digital value at a predetermined sampling rate to generate a conversion data series. An interpolation processor upsamples the outputted conversion data series by inserting interpolation data therein to generate an up-data series. A distance calculator calculates a distance to an object that reflects light using a signal waveform indicated by the up-data series. The interpolation processor inserts the interpolation data having an interpolation value between pieces of data belonging to the conversion data series, and smooths the data series in which the interpolation data is inserted using a low-pass filter that has characteristics in which waveform distortion caused by ringing does not occur.

A SAR ADC includes a first capacitor array, a first comparator, a second capacitor array, a second comparator, an arbiter and a control circuit. The first capacitor array is arranged for receiving an input signal to generate a first signal. The first comparator is arranged for comparing the first signal with a first reference signal to generate a first comparison result. The second capacitor array is arranged for receiving the input signal to generate a second signal. The second comparator is arranged for comparing the second signal with a second reference signal to generate a second comparison result. The arbiter is arranged for generating an arbitration result according to the first comparison result and the second comparison result. The control circuit is arranged for generating an output signal according to the first comparison result, the second comparison result and the arbitration result.

A cylinder-piston unit including: at least one cylinder including a tubular body (2); at least one piston (5) liable with a respective rod (5a), said piston (5) and said rod (5a) being translatable longitudinally in said tubular body (2) of said cylinder, at least one reference codification (C) extending for at least a section (dC) on the surface of said rod (5a), along the longitudinal axis of the same; at least detecting means (7), movable anchorable to said tubular body (2), faced, in use, towards said rod (5a) and suitable to detect said at least one reference codification (C) and to emit at the output at least a corresponding output electrical signal (s7), at least a reference zone (7c) of amplitude (d7c) delimited from said detecting means (7), said at least one reference codification (C) being detectable in correspondence to said at least one detection zone (7c); said at least one reference codification (C) including at least one plurality of adjacent sectors ( . . . , Si1, Si, Si+1, . . . ) extending along said longitudinal axis of said rod (5a), each of them for a section (dSi) of equal length; each sector (Si) includes a plurality of optical contrast zones (si1, si2, si3), each of them extending along said longitudinal axis of said rod (5a) for a respective section of extension (dsi1, dsi2, dsi3) such as the sum of the extensions of said sections of extensions (dsi1+dsi2 . . . ), in each sector (Si) is lower or equal to said amplitude (d7c) of said detecting zone (7c); said optical contrast zones (si1, si2, si3) being arranged in each sector (Si) according to the same sequence; and wherein in each sector (Si) at least one optical contrast zone (si1, si2, si3) shows said at least one respective section of extension (ds1, ds2, ds3) of different length compared to the length of the same section of extension in the other sectors (Si2, Si1, Si+1, Si+2, . . . ), therefore each sector (Si) remains univocally definable from the length of said at least one section of extension (dsi1, dsi2, dsi3) of said optical contrast zones (si1, si2, si3) in it included.

Aspects of the disclosure are directed to a pulse to digital converter. In accordance with one aspect, the pulse to digital converter includes an input to receive an input pulse signal; a fractional element, coupled to the input, wherein the fractional element generates a fractional pulse width measurement of the input pulse signal; and an integral element, coupled to the input, wherein the integral element generates an integral pulse width measurement of the input pulse signal, and wherein the fractional pulse width measurement and the integral pulse width measurement are concatenated as an output signal.