Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.

A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.

Disclosed are an analog-to-digital conversion circuit, an analog-to-digital conversion device, and a digital x-ray imaging system. The analog-to-digital conversion circuit includes a first reference voltage source, a second reference voltage source, a first analog-to-digital converter connected to the first reference voltage source, a second analog-to-digital converter connected to the second reference voltage source, a connecting circuit connected to the first analog-to-digital converter and the second analog-to-digital converter, respectively, and a current source having negative temperature coefficient configured to be connected to the first reference voltage source and the second reference voltage source, respectively.

The digital temperature sensing circuit includes a temperature voltage generator configured to generate a temperature voltage varying with a temperature in response to a first reference voltage, divide a supply voltage in response to a second reference voltage, and generate a high voltage and a low voltage, a code voltage generator configured to divide the second reference voltage based on the high voltage and the low voltage and output divided voltages having different voltage levels, and a mode selector supplied with the temperature voltage and the divided voltages, and configured to output a first code or a second code in response to a mode select signal, wherein the first code and the second code have different numbers of bits.

The digital temperature sensing circuit includes a temperature voltage generator configured to generate a temperature voltage varying with a temperature in response to a first reference voltage, divide a supply voltage in response to a second reference voltage, and generate a high voltage and a low voltage, a code voltage generator configured to divide the second reference voltage based on the high voltage and the low voltage and output divided voltages having different voltage levels, and a mode selector supplied with the temperature voltage and the divided voltages, and configured to output a first code or a second code in response to a mode select signal, wherein the first code and the second code have different numbers of bits.

The digital temperature sensing circuit includes a temperature voltage generator configured to generate a temperature voltage varying with a temperature in response to a first reference voltage, divide a supply voltage in response to a second reference voltage, and generate a high voltage and a low voltage, a code voltage generator configured to divide the second reference voltage based on the high voltage and the low voltage and output divided voltages having different voltage levels, and a mode selector supplied with the temperature voltage and the divided voltages, and configured to output a first code or a second code in response to a mode select signal, wherein the first code and the second code have different numbers of bits.

A successive-approximation ADC includes an input capacitance coupled to a first node and configured to store a sampled input charge based on an input analog signal during a first phase of an analog-to-digital conversion. A gain tuning capacitance configured to store a first portion of the sampled input charge during a second phase of the analog-to-digital conversion. A charge-redistribution DAC includes a conversion capacitance configured to store a second portion of the sampled input charge during the second phase and configured to use the second portion, a remaining portion of the sampled input charge, and a reference voltage to provide an analog signal on the first node corresponding to a digital output code approximating the input analog signal at an end of the third phase. The gain tuning capacitance sequesters the first portion of the sampled input charge from the charge-redistribution DAC during the third phase.

A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.

A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core.