A method for self-calibration of reference voltage drop in a Digital to Analog Converter (DAC) includes measuring each one of a plurality of thermometric weightages associated with a respective one of a plurality of thermometric bits, wherein the DAC includes a plurality of sub-binary bits and the plurality of thermometric bits. For each sequentially increasing combination of thermometric bit settings including at least two thermometric bits coupled to a high reference voltage and each sub-binary bit coupled to a low reference voltage, performing the steps of: determining a respective combined weightage correction; adding the combined weightage correction to the highest order bit of the combination of thermometric bit settings; and incrementing a number of bits of the combination of thermometric bit settings in response to the number of bits of the sequential combination being less than a total number of the plurality of thermometric bits.

A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line.

A method of weight calibration in a DAC (25) is disclosed. The DAC (25) comprises an input port (100) for receiving a sequence of digital input words (x[n]), each representing a digital input sample, and a digital control circuit (110) configured to encode each digital input word (x[n]) into a control word (z[n]) representing the same digital input sample. Each bit (Z.sub.i) in the control word (z[n]) has a corresponding bit weight (w.sub.i) and is in the following considered to adopt values in {−1, 1}. Furthermore, the DAC (25) comprises a set (120) of analog weights, each associated with a unique one of the bits (Z.sub.i) in the control word (z[n]), and summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word (Z.sub.i) weighted by the respective associated analog weights. The DAC (25) also has an output (140) for outputting the analog sample. The method comprises, during a measurement procedure, for a first set of at least one bit of the control word (z[n]), generating (300) the bits of the first set, such that a first sum of the bits in the first set weighted by their respective bit weights is, on average, above zero. Furthermore, the method comprises, during the measurement procedure, for a second set of at least one bit of the control word (z[n]), generating (310) the bits of the second set, such that a second sum of the bits in the second set weighted by their respective bit weights is, on average, below zero and such that the sum of the first sum and the second sum is, on average, equal to zero. The method also comprises detecting (330) a DC level at the output of the DAC during the measurement procedure. The method further comprises adjusting (340) at least one analog weight in response to the detected DC level. A corresponding DAC, a corresponding electronic apparatus, and a corresponding integrated circuit are also disclosed.

A digital to analog converter (DAC) includes an amplifier including a buffer of the DAC, and a resistor ladder arrangement coupled to a non-inverting input terminal of the amplifier to generate a voltage based on a digital control word. The arrangement includes a first, least-significant bit, segment arranged in one of an R-2R or unit-R configuration, a second, most-significant bit, segment including one or more units each including a second-segment-resistor having a resistor terminal coupled to a respective second switch and having a second resistance, R.sub.MSB, and a third segment including one or more third-segment-resistors coupled in parallel to the non-inverting input terminal and connected to a first reference voltage terminal. M2 designates a number of bits in the digital control word for controlling the second switches, and the third segment has a total resistance, Rsp, based on M2.

A combined I/Q DAC is provided with a plurality of sources corresponding to a plurality of selectors in which the corresponding source drives the corresponding selector with a source signal to produce a corresponding pair of in-phase and quadrature-phase analog input signals to a summation network. Each selector routes its source signal responsive to a digital value of a corresponding in-phase and quadrature-phase bit pair.

The audio circuit has a volume circuit structured to process a DSD signal that contains DSD data and a DSD clock. The volume circuit has a first shift register and a replacement circuit. The first shift register holds N bits of the DSD data. The replacement circuit replaces (N−M) bits (0≤M≤N) corresponding to a gain set value, out of N bits stored in the first shift register, with a mute bit string having a mark rate of substantially 50%.

An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency f.sub.L based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing f.sub.L with a high frequency clock having a constant frequency f.sub.H. A memory is included to store at least two counter values generating by comparing f.sub.L and f.sub.H once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

A solid state imaging element according to an embodiment includes: a converter (14) that converts an analog pixel signal read out from a pixel into a bit value, successively for each of a plurality of bits, on the basis of a threshold voltage set according to a conversion history of the bit converted before a target bit; a plurality of voltage generation units (102a and 102b) that each generate a plurality of reference voltages; and a setting unit (12d) that sets the threshold voltage using the reference voltage selected from the reference voltages generated by each of the voltage generation units on the basis of a conversion result.

A signal processing circuit includes a first sampling capacitor and a second sampling capacitor that are connected for an input signal path of an analog signal, and a signal processor configured to perform predetermined processing on the analog signal sampled by the first sampling capacitor and the analog signal sampled by the second sampling capacitor. The sampling of the analog signal transmitted to one capacitor of the first sampling capacitor and the second sampling capacitor, and the predetermined processing performed by the signal processor on the analog signal sampled by another capacitor of the first sampling capacitor and the second sampling capacitor can be performed in parallel.