A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.

An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.

An apparatus for canceling an input offset of a receiver including a differential amplification unit and a differential comparison unit in a distance sensing system includes: an output monitoring unit selectively monitoring differential outputs of the differential comparison unit and the differential amplification unit; a current type digital-analog conversion unit connected to each of an input terminal of the differential comparison unit and the input terminal of the differential amplification unit; and a control unit controlling the current type digital-analog conversion unit to reduce a difference in differential output of the differential comparison unit according to a comparison result for the difference of the monitored differential output of the differential comparison unit and controlling the current type digital-analog conversion unit to reduce the difference in differential output of the differential amplification unit according to the comparison result for the difference of the monitored differential output of the differential amplification unit.

In accordance with the present invention a system and method for calibration of the current steering DAC is elaborated which helps to reduce design complexity and reduce silicon area required in the design. Present invention is utilising a clocked comparator and plurality of switch transistors 405,305 and AUX DAC in conjunction with digital estimator and digital compensator blocks to estimate the errors in the current sources 406 and compensate the errors using same AUX DAC during normal operation mode.

An optical receiver device includes a boost converter circuit, an optical receiver circuit, and a pulse width modulation controller circuitry. The boost converter circuit is configured to convert a supply voltage according to a pulse width modulation signal, in order to generate an output voltage. The optical receiver circuit is configured to set a gain according to the output voltage, in order to convert an optical signal to a data signal according to the gain. The pulse width modulation controller circuitry is configured to perform a digital to analog conversion according to a control code to gradually adjust a current associated with the output voltage, and to compare the output voltage with a reference voltage to generate the pulse width modulation signal.

A method for determining an inverse impulse response of a communication channel by means of a PAM receiver comprises the following method steps: switching on the PAM receiver; if a second PAM transceiver is switched on, setting a difference between a clock frequency of the data signal and a sampling frequency of the first PAM transceiver; comparing a symbol that is output by the interpreter with a state that is supplied to the interpreter, and outputting an error value, wherein in each case a symbol associated with a sampling clock is compared with a state associated with the same sampling clock; adapting m filter coefficients of the equalizer to minimize error values; repeating the third method step and the fourth method step until an error limit value is reached.

Methods and apparatus for adaptively generating a reference voltage (V.sub.REF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a V.sub.REF generation circuit coupled to the regulation circuit and configured to adaptively generate a V.sub.REF for the regulation circuit.

A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.