An analog-to-digital circuit that digitizes an analog voltage. The analog-to-digital circuit includes plural comparators functionally connected to form a tree that has levels i, and each level i has branches j, and an encoder connected to the plural comparators and configured to generate a digitized value of an input analog voltage. Each comparator from a level i has first and second outputs, and each of the first and second outputs is electrically connected to an input of different comparators from a next level i+1 of the tree.

Circuitry is disclosed herein that dynamically (temperature-invariant and voltage-invariant) adjusts the Ron of switches in a resistive Nyquist-rate digital to analog converter (DAC) to thereby reduce DAC nonlinearity errors and improve INL results of greater than 16b. Consistent with the present disclosure, the DAC includes an R-2R ladder in which each bit corresponds to a switch. A control circuit is provided for generating signals applied to the gate of the switch to cause the on-resistances of the switch to be a particular value, such that the on-resistance of the switch plus the sum of two resistors, one having the resistance R, and the other having a resistance R′ is equivalent to the resistance of the 2R-size resistors or twice the resistance of the R-sized resistors in the ladder.

Circuitry is disclosed herein that dynamically (temperature-invariant and voltage-invariant) adjusts the Ron of switches in a resistive Nyquist-rate digital to analog converter (DAC) to thereby reduce DAC nonlinearity errors and improve INL results of greater than 16b. Consistent with the present disclosure, the DAC includes an R-2R ladder in which each bit corresponds to a switch. A control circuit is provided for generating signals applied to the gate of the switch to cause the on-resistances of the switch to be a particular value, such that the on-resistance of the switch plus the sum of two resistors, one having the resistance R, and the other having a resistance R′ is equivalent to the resistance of the 2R-size resistors or twice the resistance of the R-sized resistors in the ladder.

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

A control circuit and a method of calibrating a signal converter (such as DAC) are disclosed. The control circuit can be an existing control circuit, so no additional calibration circuit is required and the circuit area can be reduced. The control circuit can be an embedded microcontroller or other type of microcontroller. In general, the microcontroller includes an analog comparator and an arithmetic unit. With the combination of using the arithmetic unit to execute firmware program codes and using of the analog comparator, the control circuit is able to calibrate the signal converter.

A control circuit and a method of calibrating a signal converter (such as DAC) are disclosed. The control circuit can be an existing control circuit, so no additional calibration circuit is required and the circuit area can be reduced. The control circuit can be an embedded microcontroller or other type of microcontroller. In general, the microcontroller includes an analog comparator and an arithmetic unit. With the combination of using the arithmetic unit to execute firmware program codes and using of the analog comparator, the control circuit is able to calibrate the signal converter.

An example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.

A digital-analog converter of the disclosure converts digital image data to generate analog data signals. The digital-analog converter includes a voltage divider which generates a plurality of gamma reference voltages based on a first reference voltage and a second reference voltage; a global ramp including a plurality of gamma decoders which generates a plurality of global gamma voltages based on the gamma reference voltages; a decoder which selects one of the global gamma voltages according to the digital image data to generate the analog data signals; and a ramp controller which turns off at least some of the gamma decoders based on the digital image data.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.