An auto calibration method used in switching converters with constant on-time control. The auto calibration method includes: generating a periodical clock signal with a predetermined duty cycle; providing a first voltage and a second voltage to an on-time control circuit to generate an on-time control signal based on the first and second voltage; providing the clock signal and on-time control signal to a logic circuit to generate a switch control signal based on the clock signal and on-time control signal; comparing the duty cycle of the switch control signal with the duty cycle of the clock signal to adjust a calibration code signal; and adjusting circuit parameters of the on-time control circuit in accordance with the calibration code signal.

Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.

A computing-in-memory circuit comprises a computing element array and an analog-to-digital conversion circuit. The computing element array is utilized for analog computation operations. The computing element array includes memory cells, a first group of computing elements, and a second group of computing elements. The first group of computing elements provides capacitance for analog computation in response to an input vector and receives data from the plurality of memory cells and the input vector. The second group of computing elements provides capacitance for quantization. Each computing element of the computing element array is based on a switched-capacitors circuit. The analog-to-digital conversion circuit includes a comparator and a conversion control unit. The comparator has a signal terminal, a reference terminal, and a comparison output terminal, wherein the first and second groups of computing elements are selectively coupled to the signal terminal and the reference terminal.

A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

Device for generating analogue signals comprises a digital-to-analogue converter comprising at least one digital input and one analogue output, a circuit for generating a first clock signal of frequency fs, and a digital register configured so as to receive at the input and to store N bits representative of an analogue output signal of the converter, N being an integer greater than or equal to 1, and for receiving the first clock signal, the register comprising, for each bit, two complementary digital outputs.

A digital-to-analog converter circuit that creates an analog waveform from an input digital waveform. Operating the circuit comprises using the input digital waveform to 1) operate a charge control switch to set a charge time period, 2) operate a discharge control switch to set a discharge time period, 3) set a charge current magnitude using a charge gain, and 4) set a discharge current magnitude using a discharge gain. A charge source electrically charges a load capacitor during the charge time period (i.e., the charge mode). A discharge source electrically discharges the load capacitor during the discharge time period (i.e., the discharge mode). A circuit output transmits the analog waveform defined by the charge mode and the discharge mode. A charge current magnitude greater than the discharge current magnitude produces an upward-sloping analog waveform. A charge current magnitude less than the discharge current magnitude produces a downward-sloping analog waveform.

A calibratable switched-capacitor voltage reference and an associated calibration method are described. The voltage reference includes dynamic diode elements providing diode voltages, input capacitor(s) for sampling input voltages, base-emitter capacitor(s) for sampling one diode voltage with respect to a ground, dynamically trimmable capacitor(s) for sampling the one diode voltage with respect to another diode voltage, and an operational amplifier coupled to the capacitors for providing reference voltage(s) based on the sampled input and diode voltages and on trims of the trimmable capacitor(s). The voltage reference can be configured as a first integrator of a modulator stage of a delta-sigma analog-to-digital converter.

A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T≥2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2≤X≤T, wherein, for each value of X in the range 1≤X<T: each Xth-tier resistor is connected between a pair of nodes of the voltage-divider circuit at which a relatively high and low voltage signal are provided, respectively; at least one Xth-tier resistor is implemented as a subdivision network of discrete resistors; and for each Xth-tier resistor implemented as a subdivision network, that subdivision network includes a main resistor connected in series with a corresponding auxiliary resistor, that main resistor implemented as a base resistor connected in parallel with a series connection of a plurality of X+1th-tier resistors.

A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T≥2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2≤X≤T, wherein, for each value of X in the range 1≤X<T: each Xth-tier resistor is connected between a pair of nodes of the voltage-divider circuit at which a relatively high and low voltage signal are provided, respectively; at least one Xth-tier resistor is implemented as a subdivision network of discrete resistors; and for each Xth-tier resistor implemented as a subdivision network, that subdivision network includes a main resistor connected in series with a corresponding auxiliary resistor, that main resistor implemented as a base resistor connected in parallel with a series connection of a plurality of X+1th-tier resistors.

A digital-to-analog converter is provided. The digital-to-analog converter comprises a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter comprises a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells comprise a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells comprise different numbers of inverter cells. The digital-to-analog converter additionally comprises an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.