Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.

The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

An operating method of a memory controller is provided. The operating method includes receiving a first read data and a second conversion information, the second conversion information including data obtained by converting a second read data based on a linear operation, and the first read data and the second read data including data read from same memory cells; converting the first read data based on the linear operation to generate a first conversion information; performing a logical operation on the first conversion information and the second conversion information to generate an operation information; performing an inverse operation of the linear operation on the operation information to generate a reliability information; and correcting an error of the first read data based on the first read data and the reliability information.

The present invention is directed to data communication systems and methods thereof According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

A memory system includes a memory controller. The memory controller executes first calculation of obtaining a first degree to k-th degree error locator polynomials (1≤k<t) by using a syndrome, determines whether error locations can be calculated by the error locator polynomials up to the k-th degree, obtains an initial value of a parameter to be used for second calculation of obtaining error locator polynomials up to t-th degree when it is determined that the error locations cannot be calculated, executes the second calculation using the initial value, calculates the error locations by using an error locator polynomial determined to be able to calculate the error locations among the first degree to k-th degree error locator polynomials or by using error locator polynomials obtained in the second calculation, and corrects errors in the calculated error locations.

A method of performing division operations in an error correction code includes the steps of receiving an output ω∈F†{0} wherein F=GF(2.sup.r) is a Galois field of 2.sup.r elements, ω=Σ.sub.0≤i≤r−1β.sub.i×α.sup.i wherein α is a fixed primitive element of F, and β.sub.i∈GF(2), wherein K=GF(2.sup.s) is a subfield of F, and {1, α} is a basis of F in a linear subspace of K; choosing a primitive element δ∈K, wherein ω=ω.sub.1+α×ω.sub.2, ω.sub.1=Σ.sub.0≤i≤s−1γ.sub.i×δ.sup.i∈K, ω.sub.2=Σ.sub.0≤i≤s−1γ.sub.i+s×δ.sup.i∈K, and γ=[γ.sub.0, . . . , γ.sub.r−1].sup.T∈GF(2).sup.r; accessing a first table with ω.sub.1 to obtain ω.sub.3=ω.sub.1.sup.−1, computing ω.sub.2×ω.sub.3 in field K, accessing a second table with ω.sub.2=ω.sub.3 to obtain (1+α×ω.sub.2×ω.sub.3).sup.−1=ω.sub.4+α×ω.sub.5, wherein ω.sup.−1=(ω.sub.1×(1+α×ω.sub.2×ω.sub.3)).sup.−1=ω.sub.3×(ω.sub.4+α×ω.sub.5)=ω.sub.3×ω.sub.4+α×ω.sub.3×ω.sub.5; and computing products ω.sub.3×ω.sub.4 and ω.sub.3×ω.sub.5 to obtain ω.sup.−1=Σ.sub.0≤i≤s−1θ.sub.i×δ.sup.i+α.Math.Σ.sub.i≤i≤s−1θ.sub.i+s=δ.sup.i where θ.sub.i∈GF(2).

A Reed-Solomon decoder circuit includes: a syndrome calculator circuit to compute syndrome values for a first codeword and a second codeword sequentially supplied to the syndrome calculator circuit, where last symbols of the first codeword overlap with first symbols of the second codeword during an overlap clock cycle between: a first plurality of non-overlap clock cycles during which the first codeword is supplied to the syndrome calculator circuit; and a second plurality of non-overlap clock cycles during which the second codeword is supplied to the syndrome calculator circuit; an error locator and error evaluator polynomial calculator circuit; an error location and error value calculator circuit; an error counter; and an error corrector circuit to correct the errors in the first codeword and the second codeword based on error counts and the error magnitudes computed by an error evaluator circuit.

A multi-port, multi-mode Reed Solomon (RS) forward error correction system includes a plurality of data in lines, each associated with a data port. The system includes a syndrome block (SDM) that has a plurality of syndrome slices and a SDM switching logic. An input of a SDM slice couples with a data in line from the plurality of data in lines. The switching logic couples with an interface port width (IFW) line a mode line. The IFW line identifies a number of data in lines tied together and the mode line to identify a RS mode. A reformulated inversionless Berlekamp-Massey (RiBM) block has a plurality of RiBM slices and a RiBM switching logic. A Chien Forney (ChFr) block has a plurality of ChFr slices. An error evaluation magnitude (ErEval) block has a plurality of ErEval slices. A plurality of adders couple with an output of a corresponding ErEval slice.

Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.

A method of performing division operations in an error correction code includes the steps of receiving an output ω∈F†{0} wherein F=GF(2.sup.r) is a Galois field of 2.sup.r elements, ω=Σ.sub.0≤i≤r−1β.sub.i×α.sup.i wherein α is a fixed primitive element of F, and β.sub.i∈GF(2), wherein K=GF(2.sup.s) is a subfield of F, and {1, α} is a basis of F in a linear subspace of K; choosing a primitive element δ∈K, wherein ω=ω.sub.1+α×ω.sub.2, ω.sub.1=Σ.sub.0≤i≤s−1 γ.sub.i×δ.sup.i∈K, ω.sub.2=Σ.sub.0≤i≤s−1 γ.sub.i+s×δ.sup.i∈K, and γ=[γ.sub.0, . . . , γ.sub.r−1].sup.T∈GF(2).sup.r; accessing a first table with ω.sub.1 to obtain ω.sub.3=ω.sub.1.sup.−1, computing ω.sub.2×ω.sub.3 in field K, accessing a second table with ω.sub.2=ω.sub.3 to obtain (1+α×ω.sub.2×ω.sub.3).sup.−1=ω.sub.4+α×ω.sub.5, wherein ω.sup.−1=(ω.sub.1×(1+α×ω.sub.2×ω.sub.3)).sup.−1=ω.sub.3×(ω.sub.4+α×ω.sub.5)=ω.sub.3×ω.sub.4+α×ω.sub.3×ω.sub.5; and computing products ω.sub.3×ω.sub.4 and ω.sub.3×ω.sub.5 to obtain ω.sup.−1=Σ.sub.0≤i≤s−1θ.sub.i×δ.sup.i+α.Math.Σ.sub.i≤i≤s−1θ.sub.i+s=δ.sup.i where θ.sub.i∈GF(2).