Techniques for using erasure coding in a single region to reduce the likelihood of losing objects in a cloud object storage platform are provided. In one set of embodiments, a computer system can upload a plurality of data objects to a region of a cloud object storage platform, where the plurality of data objects including modifications to a data set. The computer system can further compute a parity object based on the plurality of data objects, where the parity object encodes parity information for the plurality of data objects. The computer system can then upload the parity object to the same region where the plurality of data objects was uploaded.

A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.

A method includes receiving, at a first computing device, a first input/output (TO) command from a first artificial intelligence processing unit (AI PU), the first TO command associated with a first AI model training operation. The method further includes receiving, at the first computing device, a second TO command from a second AI PU, the second TO command associated with a second AI model training operation. The method further includes assigning a first timestamp to the first TO command based on a first bandwidth assigned to the first AI model training operation. The method further includes assigning a second timestamp to the second TO command based on a second bandwidth assigned to the second AI model training operation.

Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.

A quantum computing system for converting Pauli errors of one or more qubits to erasure errors in a photonic quantum computing architecture. Two or more photonic qubits may be input to a quantum computing system, where at least one first qubit of the two or more qubits has experienced a Pauli error. A sequence of linear optical circuitry operations may be performed on the two or more qubits to generate two or more modified qubits, wherein the sequence of operations transforms one or more of the first qubits from a logical subspace of a Fock space to an erasure subspace of the Fock space. A cluster state for universal quantum computing may be generated from the two or more modified qubits using probabilistic entangling gates. A quantum computational algorithm may be performed using the quantum cluster state generated from the two or more modified qubits.

In one embodiment, a method includes applying Forward Error Correction (FEC) to data at power sourcing equipment, transmitting the data and pulse power over a wire pair to a powered device, identifying data transmitted during power transitions between a pulse power on time and a pulse power off time in the pulse power at the powered device, and applying FEC decoding to at least a portion of the data based on said identified power transitions.

A technique provides efficient data protection, such as erasure coding, for data blocks of volumes served by storage nodes of a cluster. Data blocks associated with write requests of unpredictable client workload patterns may be compressed. A set of the compressed data blocks may be selected to form a write group and an erasure code may be applied to the group to algorithmically generate one or more encoded blocks in addition to the data blocks. Due to the unpredictability of the data workload patterns, the compressed data blocks may have varying sizes. A pool of the various-sized compressed data blocks may be established and maintained from which the data blocks of the write group are selected. Establishment and maintenance of the pool enables selection of compressed data blocks that are substantially close to the same size and, thus, that require minimal padding.

A hardware architecture for systematic erasure encoding includes first matrix constructor circuit that receives parity-check matrix H for codeword C, and the erased part of codeword C, and outputs matrix H.sub.1 of columns of H located on erased coordinates of code C; second matrix constructor circuit that receives matrix H and the erased part of codeword C and outputs matrix H.sub.2 of columns of H located on non-erased coordinates of code C; a neural network that calculates matrix J.sub.1 that is an approximate inverse of matrix H.sub.1. The matrix J.sub.1 is used to determine new erasures in the parity matrix H and new erased coordinates. Matrices H.sub.1 and H.sub.2 are updated, and the updated H.sub.1 is provided as feedback to the first matrix constructor circuit. A calculator circuit restores the erased coordinates of codeword C, from the matrix J.sub.1, matrix H.sub.2, and a non-erased part of codeword C.

A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

A transmitter may be configured to determine a coding rate at which to encode data packets based on a quantity of encoded packets used by a receiver for recovery of one data packet. The transmitter may be further configured to transmit a set of encoded packets generated at the coding rate to the receiver. The receiver may be configured to receive, from the transmitter, encoded packets carrying a set of data packets encoded at a coding rate. The receiver may be further configured to transmit, to the transmitter, feedback indicating a quantity of a set of the encoded packets used for recovery of one data packet of the set of data packets. The receiver may be further configured to receive, from the transmitter, other encoded packets carrying another set of data packets encoded at another coding rate.