A method for reconstructing uncorrectable forward error correction (FEC) data includes generating and transcoding a known bit sequence and transmitting a FEC encoded codeword that includes a payload containing the transcoded known bit sequence through a component under test. The method further includes receiving the FEC encoded codeword transmitted via the component under test and determining that the encoded contents of the FEC encoded codeword contains a number of symbol errors that exceeds a predefined threshold. The method also includes utilizing stored scramble seed bits corresponding to an immediately preceding FEC encoded codeword and the transcoded known bit sequence to generate a reconstructed codeword.

A method for reconstructing uncorrectable forward error correction (FEC) data includes generating and transcoding a known bit sequence and transmitting a FEC encoded codeword that includes a payload containing the transcoded known bit sequence through a component under test. The method further includes receiving the FEC encoded codeword transmitted via the component under test and determining that the encoded contents of the FEC encoded codeword contains a number of symbol errors that exceeds a predefined threshold. The method also includes utilizing stored scramble seed bits corresponding to an immediately preceding FEC encoded codeword and the transcoded known bit sequence to generate a reconstructed codeword.

A memory system of an embodiment includes a non-volatile memory and a memory controller. The memory controller executes a first decoding process of reading data encoded by an error correction code from the non-volatile memory and repeatedly executing bounded distance decoding on a symbol group protected by each of component codes included in N component code groups; executes a second decoding process of repeatedly executing decoding exceeding a bounded distance in units of component codes for an error symbol group determined to include an error due to a syndrome of a component code included in the N component code groups when the first decoding process fails; executes a rollback process when the first decoding process executed after the second decoding process fails; and changes a parameter used in the second decoding process and further executes the second decoding process when it is detected that the second decoding process is not progressed.

A method for generating a signal, including turbo-coding a set of information symbols delivering, on the one hand, the information symbols and, on the other hand, redundancy symbols. The turbo-coding implementing, to obtain the redundancy symbols: an encoding of the set of information symbols by a first encoder, an interleaving of the set of information symbols, and an encoding of the set of information symbols interleaved by a second encoder. The turbo-coding also implements a bijective transformation of the information symbols, implemented before and/or after the interleaving, the transformation modifying a value of at least two of the information symbols prior to the coding of the information symbols by the first and/or the second coder.

A method for generating a signal, including turbo-coding a set of information symbols delivering, on the one hand, the information symbols and, on the other hand, redundancy symbols. The turbo-coding implementing, to obtain the redundancy symbols: an encoding of the set of information symbols by a first encoder, an interleaving of the set of information symbols, and an encoding of the set of information symbols interleaved by a second encoder. The turbo-coding also implements a bijective transformation of the information symbols, implemented before and/or after the interleaving, the transformation modifying a value of at least two of the information symbols prior to the coding of the information symbols by the first and/or the second coder.

A memory system of an embodiment includes a non-volatile memory and a memory controller. The memory controller executes a first decoding process of reading data encoded by an error correction code from the non-volatile memory and repeatedly executing bounded distance decoding on a symbol group protected by each of component codes included in N component code groups; executes a second decoding process of repeatedly executing decoding exceeding a bounded distance in units of component codes for an error symbol group determined to include an error due to a syndrome of a component code included in the N component code groups when the first decoding process fails; executes a rollback process when the first decoding process executed after the second decoding process fails; and changes a parameter used in the second decoding process and further executes the second decoding process when it is detected that the second decoding process is not progressed.

Embodiments of the present disclosure provide a high speed low latency rate configurable soft decision and hard decision based pipelined Reed-Solomon (RS) decoder architecture suitable for optical communication and storage. The proposed RS decoder is a configurable RS decoder that is configured to monitor the channel and adjust code parameters based on channel capacity. The proposed RS decoder includes interpolation and factorization free Low-Complexity-Chase (LCC) decoding to implement soft-decision decoder (SDD). The proposed RS decoder generates test vectors and feeds these to a pipelined 2-stage hard decision decoder (HDD). The proposed RS decoder architecture computes error locator polynomial in exactly 2t clock cycles without parallelism and supports high throughput, and further computes error evaluator polynomial in exactly t cycles. The present disclosure provides a 2-stage pipelined decoder to operate at least latency possible and reduced size of delay buffer.

Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.

Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.

In various embodiments, a method for determining an error vector in a data word is provided. The method includes determining the syndrome of the error vector, successively generating code words by cyclically interchanging one or more predefined code words, forming, for each code word generated, the sum of the syndrome supplemented with zeros to the data word length and the code word, and checking, for the code word, whether the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words, and determining the error vector as the sum of the syndrome and the code word for which the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words.