A decoding apparatus includes input circuitry configured to receive coded data; and decoding circuitry configured to decode the coded data to obtain decoded data. The coded data are generated by using an encoding process at an encoding apparatus. The encoding process includes: (i) repeatedly collecting first data blocks included in the decoded data to generate at least one second data block; (ii) dividing at least one third data block included in the decoded data into fourth data blocks; (iii) allocating fifth data blocks included in the decoded data to respective sixth data blocks without collecting the first data blocks or dividing the at least one third data block; and (iv) performing an error correcting encoding on the at least one second data block, the fourth data blocks, and the sixth data blocks in accordance with a coding rate selected from a plurality of coding rates to generate parity data.

An error correction and fault tolerance method and system for an array of disks is presented. The array comprises k+5 disks, where k disks store user data and 5 disks store computed parity. The present invention further comprises a method and a system for reconstituting the original content of each of the k+5 disks, when up to 5 disks have been lost, wherein the number of disks at unknown locations is E and the number of disks wherein the location of the disks is known is Z. All combinations of faulty disks wherein Z+2×E≤4 are reconstituted. Some combinations of faulty disks wherein Z+2×E≥5 are either reconstituted, or errors are limited to a small list.

An ECC decoder includes a syndrome calculation block, a fast path controller, a KES block, a CSEE block, an UED, and a multiplexer. The KES block includes a plurality of KES-stages to calculate and output an error location/magnitude polynomial of a syndrome outputted from the syndrome calculation block. Each of a second to last KES-stages of the plurality of KES-stages receives the error location/magnitude polynomial from the previous KES-stage to output an error location/magnitude polynomial generated by an additional calculating operation. The additionally calculated error location/magnitude polynomial is not transmitted to the next KES-stage but directly outputted when an error location and an error magnitude are identified by the additionally calculated error location/magnitude polynomial.

A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.

Systems and methods are provided for quantum error correction. A quantum system includes an array of qubits configured to store an item of quantum information. The array of qubits includes a plurality of data qubits and a plurality of measurement qubits configured to extract a syndrome representing agreement among the plurality of data qubits. The quantum system further includes an integrated circuit comprising validation logic configured to determine if the syndrome is valid, decoding logic configured to determine evaluate the syndrome to determine location of errors within the plurality of data qubits, and an error register configured to store locations of the determined errors.

A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.

A method for constructing an n-qubit fault tolerant encode for any k-qubit quantum gate M, in any given quantum code [n, k, C], comprising: choosing a number n−k of independent spinors S.sub.r from the first stabilizer C and a first ordered set S.sub.C consists of the independent spinors S.sub.r; choosing a number n−k of independent spinors Ŝ.sub.r from a second stabilizer Ĉ in the intrinsic coordinate and a second ordered set Ŝ.sub.r consists of the independent spinors Ŝ.sub.r consist; implementing an encoding Q.sub.en, wherein the encoding Q.sub.en converts the first ordered set S.sub.C to the second ordered set S.sub.Ĉ, wherein the encoding Q.sub.en is a sequential product provided by sequential operations of a number n−k of unitary operators Q.sub.r; wherein each of the unitary operator Q.sub.r is composed of a single s-rotation or a product of two s-rotations; and wherein the encoding Q.sub.en converts and maps the r.sup.th independent spinor S.sub.r in the first ordered set S.sub.C to the r.sup.th independent spinor Ŝ.sub.r in the second ordered set S.sub.Ĉ correspondingly; a fault tolerant action .Math. in the quantum code [n, k, C] generated by the second stabilizer Ĉ in the intrinsic coordinate, wherein the fault tolerant action .Math. is a direct sum of a basis state operator Λ and a correction operator Ω; and acquiring a fault tolerant encode in the quantum code [n, k, C] generated by the first stabilizer C, wherein the fault tolerant encode is a sequential product of the encoding Q.sub.en, the fault tolerant action .Math. and a complex conjugate Q.sub.en.sup.† of the encoding Q.sub.en.

A method of performing division operations in an error correction code includes the steps of receiving an output ω∈F†{0} wherein F=GF(2.sup.r) is a Galois field of 2.sup.r elements, ω=Σ.sub.0≤i≤r−1β.sub.i×α.sup.i wherein α is a fixed primitive element of F, and β.sub.i∈GF(2), wherein K=GF(2.sup.s) is a subfield of F, and {1, α} is a basis of F in a linear subspace of K; choosing a primitive element δ∈K, wherein ω=ω.sub.1+α×ω.sub.2, ω.sub.1=Σ.sub.0≤i≤s−1γ.sub.i×δ.sup.i∈K, ω.sub.2=Σ.sub.0≤i≤s−1γ.sub.i+s×δ.sup.i∈K, and γ=[γ.sub.0, . . . , γ.sub.r−1].sup.T∈GF(2).sup.r; accessing a first table with ω.sub.1 to obtain ω.sub.3=ω.sub.1.sup.−1, computing ω.sub.2×ω.sub.3 in field K, accessing a second table with ω.sub.2=ω.sub.3 to obtain (1+α×ω.sub.2×ω.sub.3).sup.−1=ω.sub.4+α×ω.sub.5, wherein ω.sup.−1=(ω.sub.1×(1+α×ω.sub.2×ω.sub.3)).sup.−1=ω.sub.3×(ω.sub.4+α×ω.sub.5)=ω.sub.3×ω.sub.4+α×ω.sub.3×ω.sub.5; and computing products ω.sub.3×ω.sub.4 and ω.sub.3×ω.sub.5 to obtain ω.sup.−1=Σ.sub.0≤i≤s−1θ.sub.i×δ.sup.i+α.Math.Σ.sub.i≤i≤s−1θ.sub.i+s=δ.sup.i where θ.sub.i∈GF(2).

A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

An ECC decoder includes a syndrome calculation block, a fast path controller, a KES block, a CSEE block, an UED, and a multiplexer. The KES block includes a plurality of KES-stages to calculate and output an error location/magnitude polynomial of a syndrome outputted from the syndrome calculation block. Each of a second to last KES-stages of the plurality of KES-stages receives the error location/magnitude polynomial from the previous KES-stage to output an error location/magnitude polynomial generated by an additional calculating operation. The additionally calculated error location/magnitude polynomial is not transmitted to the next KES-stage but directly outputted when an error location and an error magnitude are identified by the additionally calculated error location/magnitude polynomial.