H03M13/2732

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

Syndrome calculation for error detection and error correction
11711100 · 2023-07-25 · ·

A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.

Device for generating broadcast signal frame and method for generating broadcast signal frame corresponding to time interleaver for supporting plurality of operation modes

An apparatus and method for generating a broadcast signal frame corresponding to a time interleaver supporting a plurality of operation modes are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and the time interleaver performs the interleaving by using one of a plurality of operation modes.

Efficient interleaver design for polar codes
11558149 · 2023-01-17 · ·

Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns, where the number of columns of the interleaver varies between the rows. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a trapezoid-shaped matrix of rows and columns.

TIME INTERLEAVER, TIME DEINTERLEAVER, TIME INTERLEAVING METHOD, AND TIME DEINTERLEAVING METHOD
20230216807 · 2023-07-06 ·

A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

CONVOLUTION TIME DE-INTERLEAVER AND METHOD FOR OPERATING A CONVOLUTION TIME DE-INTERLEAVER
20220413747 · 2022-12-29 ·

A convolution time de-interleaver includes an input buffer, an output buffer, a memory, an input control circuit, an output control circuit, and a controller. The memory includes a plurality of memory blocks. The input control circuit sequentially outputs a plurality of entries of data to a plurality of input register unit groups of the input buffer respectively and correspondingly. After a predetermined amount of data have been written to the input buffer, the controller writes part of data stored in the input buffer to a corresponding memory block. After the plurality of memory blocks are written, the controller writes data stored in a corresponding memory block to the output buffer. The output control circuit sequentially outputs a plurality of pieces of data stored in a plurality of output register unit groups of the output buffer.

Physical layer key based interleaving for secure wireless communication

A key-based interleaver for enhancement the security of wireless communication includes a physical layer communication channel key to provide security even when the software encryption key is compromised. A method of creating a secure communication link using a physical layer interleaving system includes implementing a key policy implementation that utilizes temporal dependency and interleaving bits using a flexible inter and intra-block data interleaver.

TIME INTERLEAVER, TIME DEINTERLEAVER, TIME INTERLEAVING METHOD, AND TIME DEINTERLEAVING METHOD
20220393991 · 2022-12-08 ·

A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

BROADCAST SIGNAL FRAME GENERATION DEVICE AND BROADCAST SIGNAL FRAME GENERATION METHOD, WHICH USE ENHANCED LAYER PHYSICAL LAYER PIPE

An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time-interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling start position information and size information for each of Physical Layer Pipes (PLPs). In this case, the Physical Layer Pipes include a core layer physical layer pipe corresponding to the core layer signal and an enhanced layer physical layer pipe corresponding to the enhanced layer signal.

SPATIALLY COUPLED FORWARD ERROR CORRECTION ENCODING METHOD AND DEVICE USING GENERALIZED ERROR LOCATING CODES AS COMPONENT CODES

The present disclosure provides an encoding and decoding device implementing an improved forward error correction (FEC) coding/decoding method. In particular, the encoding device is configured to encode a stream of data symbols using a spatially coupled code (e.g. staircase codes, braided block codes or continuously interleaved block codes), wherein at least one generalized error location (GEL) code is used as a component code of the spatially coupled code. Accordingly, the decoding device is configured to decode a sequence of encoded symbol blocks using a spatially coupled code, wherein at least one GEL code is used as a component code of the spatially coupled code. Thereby, a suitable spatially coupled FEC code that allows for very low-latency, high-throughput, high-rate applications with a low-complexity decoding procedure, and allows for mitigation of the error-floor, is designed.