The invention relates to an interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. Each stage includes switching elements having input pins and output pins. The input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals. The input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage.

A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.

A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.

The invention relates to an interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. Each stage includes switching elements having input pins and output pins. The input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals. The input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage. The interconnection network is operable to route, on the basis of routing commands applied to the switching elements, N input values received at the N input terminals through the M stages and the interconnection sub-networks to provide, at the N output terminals, N output values corresponding to, or circularly shifted with respect to, said N input values received at the N input terminals. Additionally, M denotes a number of given submultiples of N whose product is equal to N. Each stage is associated with a respective submultiple of said M given submultiples of N, and includes S.sub.i switching elements, each having sm.sub.i respective input pins and sm.sub.i respective output pins, wherein S.sub.i=N/sm.sub.i, wherein sm.sub.i denotes the respective submultiple associated with the stage, and wherein i denotes the stage and is a positive integer comprised between one and M.

Embodiments of the present invention disclose a data transmission method, device, and system, are applied to the field of communications, and can improve data transmission efficiency and reduce a time delay. The method includes: acquiring, by a sending device, a time-frequency resource and interleaver information that are to be used by to-be-sent data, where the interleaver information includes a correspondence between an interleaver and a time synchronization code, and there is a one-to-one correspondence between a time synchronization code and an interleaver; selecting a time synchronization code and an interleaver for the to-be-sent data according to the interleaver information; and performing interleaving processing on the to-be-sent data by using the selected interleaver, and sending, to a receiving device on the time-frequency resource, the interleaved to-be-sent data that carries the selected time synchronization code. The embodiments of the present invention are applied to data transmission.

A turbo decoder decodes encoded data using a regenerated interleaver sequence. An addressable column index memory stores column indexes of the encoded data during an input phase of a turbo decode operation. An address generator generates the regenerated interleaver sequence based on the column indexes and computed data. In embodiments the address generator can read column indexes from the addressable column index memory, compute the computed data by permuting row indexes in a same row permuting order as an encoder that encoded the encoded data, combine the column indexes so read and the row indexes so permuted, use a row counter, and identify out of bounds addresses using the regenerated interleaver sequence.

Techniques are disclosed relating to circuitry configured to interleave data, e.g., for use to process error correcting codes for wireless data transmission. In some embodiments an apparatus includes one or more circuit elements configured to receive input data samples, a plurality of polynomial coefficients, a start index, and information indicating a window size for non-sequential traversal of interleaver indices. The polynomial coefficients may include coefficients for at least a third-order polynomial. In some embodiments, the one or more circuit elements are further configured to generate interleaved bank and address information for writing the input data samples to the plurality of memory blocks, based on an order of the polynomial, a code block length, the start index, and the information indicating the window size. In some embodiments, the apparatus also includes output circuitry configured to provide interleaved data samples from the memory blocks.

A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with LDPC codes. The device includes memory banks (B0 . . . Bm-1) for storing data coming from or going to the processing elements, an interconnection network (INT) for directing the data between the processing elements and the memory banks, and a control unit (CTRL) for controlling the interconnection network and the memory banks. The control unit (CTRL) includes a calculation circuit (CAL) capable of the online generation of command words for the interconnection network and addressing and control sequences of the memory banks, ensuring conflict-free memory access on the basis of the interleaving rule to be applied, the size of the digital data frames, the number of processing units and memory banks, and the interconnection network.

Techniques are disclosed relating to circuitry configured to interleave data, e.g., for use to process error correcting codes for wireless data transmission. In some embodiments an apparatus includes one or more circuit elements configured to receive input data samples, a plurality of polynomial coefficients, a start index, and information indicating a window size for non-sequential traversal of interleaver indices. The polynomial coefficients may include coefficients for at least a third-order polynomial. In some embodiments, the one or more circuit elements are further configured to generate interleaved bank and address information for writing the input data samples to the plurality of memory blocks, based on an order of the polynomial, a code block length, the start index, and the information indicating the window size. In some embodiments, the apparatus also includes output circuitry configured to provide interleaved data samples from the memory blocks.

A method for transmitting data using a convolutional turbo code (CTC) encoder. Specifically, the method comprises: encoding input data bits, which have been input through two input ports of the CTC encoder; interleaving the input data bits using four CTC interleaver parameters P.sub.0, P.sub.1, P.sub.2 and P.sub.3 corresponding to sizes of the input data bits; encoding the interleaved data bits; and selectively transmitting the input data bits, the first encoded bits and the second encoded bits, in accordance with a predetermined coding rate. Here, P.sub.0 is a relative prime number to N, which is of the size of each of the input data bits, P.sub.2 has a value of N1, and an absolute value of a difference between P.sub.1 and P.sub.3 is 1.