A method and system for error checking in a wireless communication are provided. The method includes: receiving a payload; determining a final decoding result of the payload, the final decoding result indicating a start state and an end state; determining whether the end state is identical to the start state based on a state circularity check; and determining to discard the final decoding result based on whether the end state is identical to the start state.

The present disclosure discloses a new coding scheme, which is constructed by superimposing together a pair of basic codes in a twisted manner. A SCL decoding algorithm is proposed for the TPST codes, which may be early terminated by a preset threshold on the empirical divergence functions (EDF) to trade off performance with decoding complexity. The SCL decoding of TPST is based on the efficient list decoding of the basic codes, where the correct candidate codeword in the decoding list is distinguished by employing a typicality-based statistical learning aided decoding algorithm. Lower bounds for the two layers of TPST are derived, which may be used to predict the decoding performance and to show the near-ML performance of the proposed SCL decoding algorithm. The construction of TPST codes may be generalised by allowing different basic codes for the two layers.

The present disclosure discloses a new coding scheme, which is constructed by superimposing together a pair of basic codes in a twisted manner. A SCL decoding algorithm is proposed for the TPST codes, which may be early terminated by a preset threshold on the empirical divergence functions (EDF) to trade off performance with decoding complexity. The SCL decoding of TPST is based on the efficient list decoding of the basic codes, where the correct candidate codeword in the decoding list is distinguished by employing a typicality-based statistical learning aided decoding algorithm. Lower bounds for the two layers of TPST are derived, which may be used to predict the decoding performance and to show the near-ML performance of the proposed SCL decoding algorithm. The construction of TPST codes may be generalised by allowing different basic codes for the two layers.

The present invention discloses a decoding path selection device for decoding codewords generated by convolutional codes or turbo codes encoders in error correction codes, the decoding path selection device comprising: a branch metrics calculation unit for receiving incoming signals and calculating branch metrics values; a programmable generalized trellis router for generating a decoding path control signal according to the turbo code or convolutional code specification employed by one of communications standards; a multiplexer for receiving the branch metrics values from the branch metrics calculation unit and the decoding path control signal from the programmable generalized trellis router and selecting a corresponding branch metrics value; a recursive calculation unit, connected after the multiplexer and for receiving the corresponding branch metrics value from the multiplexer; and an a-posteriori probability calculation unit, connected after the recursive calculation unit and for calculating a final decoding result.

An apparatus and method for optimizing the performance of satellite communication system receivers by using the Soft-Input Soft-Output (SISO) BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm to detect a transmitted information sequence is disclosed. A Sliding Window technique is used with a plurality of reduced state sequence estimation (RSSE) equalizers to execute the BCJR algorithm in parallel. A serial data stream is converted into a plurality of data blocks using a serial-to-parallel converter. After processing in parallel by the equalizers, the output blocks are converted back to a serial data stream by a parallel-to-serial converter. A path history is determined using maximum likelihood (ML) path history calculation.

An error correction circuit includes: a first error correction encoder for generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages; a second error correction encoder for generating a plurality of column-codewords; a first error correction decoder for performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and outputting a soft information of the first error correction decoding; and a second error correction decoder for determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.

A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.

A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.

A deep neural network (DNN) media noise predictor configured for one-dimensional-magnetic (1DMR) recording or two-dimensional-magnetic (TDMR) is introduced. Such architectures are often combined with a trellis-based intersymbol interference (ISI) detection component in a turbo architecture to avoid the state explosion problem by separating the inter-symbol interference (ISI) detection and media noise estimation into two separate detectors and uses the turbo-principle to exchange information between them so as to address the modeling problem by way of training a DNN-based media noise estimators. Thus, beneficial aspects include a reduced bit-error rate (BER), an increased areal density, and a reduction in computational complexity and computational time.

A decoding method performed by a receive end device is disclosed. The decoding method includes: receiving a first bit signal; performing level-M forward error correction (FEC) decoding on the first bit signal to obtain a second bit signal, where M is a positive integer greater than zero; checking the second bit signal to obtain a first check result; performing level-(M+1) FEC decoding on the second bit signal based on the first check result to obtain a third bit signal; and, upon determining that M+1 reaches a first preset threshold, performing data processing on the third bit signal to obtain a fourth bit signal, where the fourth bit signal is used by the receive end device to obtain service data transmitted by a transmit end device.