A cyclo-stationary characteristic of a communications channel and/or storage media is determined. The cyclo-stationary characteristic has K-cycles, K > 1. Markov transition probabilities are determined that depend on a discrete phase ϕ=t mod K, wherein t is a discrete time value. An encoder to optimize the Markov transition probabilities for encoding data sent through the communications channel and/or stored on the storage media. The optimized Markov transition probabilities are used to decode the data from the communication channel and/or read from the storage media.

The present disclosure includes apparatus, systems, and techniques relating to noise-predictive detector adaptation. A described technique includes operating a decoder system to decode codewords that are based on a received encoded signal by processing the codewords and exchanging information between path and code decoders, operating the path decoder to use estimation parameters to produce first and second paths based on a codeword of the codewords, operating the code decoder to produce a decoded path based on the codeword; determining a winning path of first and second paths based on whether the decoded path matches the first path or the second path; and updating, based on one or more error terms and the winning path, the estimation parameters to favor selection of the winning path by the path decoder and to disfavor selection of a losing path of the first and second paths by the path decoder.

Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.

A receiver for a passive optical network is provided. The receiver includes an analog-to-digital converter circuitry configured generate a digital receive signal based on an analog receive signal. The analog receive signal is based on an optical receive signal encoded with a binary transmit sequence. The receiver additionally comprises linear equalizer circuitry configured to generate an equalized receive signal by linearly equalizing the digital receive signal. Further, the receiver comprises secondary equalizer circuitry configured to generate soft information indicating a respective reliability of elements in the equalized receive signal using the Viterbi algorithm. In addition, the receiver comprises decoder circuitry configured to generate a digital output signal based on the soft information using soft decision forward error correction.

An apparatus may include a circuit configured to receive an input signal at an input and process the input signal using a set of channel parameters. The circuit may further determine an error metric for the processing of the input signal using the set of channel parameters, compare the error metric to a plurality of thresholds, and when the error metric matches one of the plurality of thresholds, adapt, using an adaptation algorithm, the set of channel parameters to produce an updated set of channel parameters for use by the circuit as the set of channel parameters in subsequent processing of the input signal, the adaptation of the set of channel parameters being based on a weight corresponding to the matching threshold of the plurality of thresholds.

An iterative decoding circuit is provided. The iterative decoding circuit includes a first concatenated decoding circuit, a second concatenated decoding circuit, and a comparator. The first concatenated decoding circuit includes a first convolutional decoder, a first deinterleaver, and a first block decoder. The second concatenated decoding circuit is coupled to the first concatenated decoding circuit, and the second concatenated decoding circuit includes a second convolutional decoder, a second deinterleaver, and a second block decoder. The comparator receives a first convolutional decoding result corresponding to a first convolutional decoding operation and a second convolutional decoding result of a second convolutional decoding operation, and is configured to compare the first convolutional decoding result with the second convolutional decoding result to generate a comparing result. The second block decoder obtains an erasure address information according to the comparing result.

Systems and methods are disclosed for phase locking multiple clocks of different frequencies. In certain embodiments, an apparatus may be configured to downsample a first clock having a first frequency and a second clock having a second frequency into downsampled clocks having the same frequency. The apparatus may adjust a frequency of the second clock so that the downsampled clocks are phase aligned. The apparatus may reset counters of the divider circuits that perform the downsampling so align them to a counter for the first clock. A counter for the second clock may also be reset to align with the counter for the first clock. The synchronized clocks may be applied in data storage operations, such as self-servo writing operations, where the first clock may be a read clock and the second clock may be a write clock.

An iterative decoding circuit is provided. The iterative decoding circuit includes a first concatenated decoding circuit, a second concatenated decoding circuit, and a comparator. The first concatenated decoding circuit includes a first convolutional decoder, a first deinterleaver, and a first block decoder. The second concatenated decoding circuit is coupled to the first concatenated decoding circuit, and the second concatenated decoding circuit includes a second convolutional decoder, a second deinterleaver, and a second block decoder. The comparator receives a first convolutional decoding result corresponding to a first convolutional decoding operation and a second convolutional decoding result of a second convolutional decoding operation, and is configured to compare the first convolutional decoding result with the second convolutional decoding result to generate a comparing result. The second block decoder obtains an erasure address information according to the comparing result.

An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

An apparatus can include a circuit configured to process an input signal using a set of channel parameters. The circuit can produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit can further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit can perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.