Designs of controllers for flash memory array are described. A controller is designed to form data packs of a predefined size with compressed data segments in different sizes. The data packs are encoded with ECC in two dimensions. When the data packs are read out, the ECC is applied in two dimensions, possibly repeated, to detect and correct errors that can be corrected by the ECC.

One embodiment provides a system which facilitates data management. During operation, the system receives, by a storage device, a plurality of data blocks. The system compresses the data blocks to obtain compressed data blocks, and performs error correction code (ECC)-encoding on the compressed data blocks to obtain ECC-encoded data blocks. The system stores the ECC-encoded data blocks in a buffer prior to writing the ECC-encoded data blocks in a non-volatile memory of the storage device, and reorganizes an order of the ECC-encoded data blocks in the buffer to match a size of a physical page of the non-volatile memory. Responsive to a first set of the reorganized ECC-encoded data blocks filling a first physical page, the system writes the first set of the reorganized ECC-encoded data blocks to the first physical page.

Designs of controllers for flash memory array are described. A controller is designed to form data packs of a predefined size with compressed data segments in different sizes. The data packs are encoded with ECC in two dimensions. When the data packs are read out, the ECC is applied in two dimensions to detect and correct errors that can be corrected by the ECC.

One embodiment provides a system which facilitates data management. During operation, the system receives, by a storage device, a plurality of data blocks. The system compresses the data blocks to obtain compressed data blocks, and performs error correction code (ECC)-encoding on the compressed data blocks to obtain ECC-encoded data blocks. The system stores the ECC-encoded data blocks in a buffer prior to writing the ECC-encoded data blocks in a non-volatile memory of the storage device, and reorganizes an order of the ECC-encoded data blocks in the buffer to match a size of a physical page of the non-volatile memory. Responsive to a first set of the reorganized ECC-encoded data blocks filling a first physical page, the system writes the first set of the reorganized ECC-encoded data blocks to the first physical page.

Embodiments of this application provide a polar code encoding and decoding method and apparatus. The method includes: obtaining an information bit set from a polar code construction sequence table based on an information bit length and a target code length of to-be-encoded information, where the polar code construction sequence table stores a mapping relationship between an encoding parameter and a construction sequence corresponding to the encoding parameter, the construction sequence is a sequence representing an order of reliability of polarized channels, and the encoding parameter includes at least one of an aggregation level, the target code length, and a mother code length, or the encoding parameter is a maximum mother code length; and performing polarization encoding on the to-be-encoded information based on the to-be-encoded information and the information bit set.

Methods, systems, and devices for wireless communications are described. The described techniques provide for generating, by an encoding device, one or more entropy symbols, the length of which changes responsive to errors, stacking the entropy symbols into fixed intervals, and selecting a parity bit. The encoding device may divide entropy symbols that are longer than the fixed interval duration and stack the excess portions of the long entropy symbols with shorter entropy symbols in other intervals. The encoding device may transmit the slacked data packet according to the stacking. A decoding device may receive the data packet, identify the locations of the entropy symbols and the selected parity bit, check the parity of each entropy symbol, identify error bits based on the locations of the entropy symbols within multiple fixed intervals, and may correct error bits based on the stacked intervals, the parity bit, and an error mask.

A flash memory controller is configured to decode a codeword. During the decoding process, the flash memory can check the decoding status of each codeword segment in the codeword and skip the decoding of a codeword segment whose decoding status is passed, thereby saving time decoding and also improving decoding efficiency. Even though only a part of the codeword segments in the codeword have been successfully decoded in the decoding process at the previous time, the flash memory controller can replace the part of the codeword segments in the codeword with the correct results obtained previously, and then decoding the re-formed codeword again. Accordingly, the decoding accuracy can be increased and the burden on the subsequent decoding process or data recovery can be reduced.

Information reduction in data processing environments includes at least one of: one or more Error Correcting Codes that decode n-vectors into k-vectors and utilize said decoding to information-reduce data from a higher dimensional space into a lower dimensional space. The information reduction further provides for a hierarchy of information reduction allowing a variety of information reductions. Transformations are provided to utilize available data space, and data may be transformed using several techniques including windowing functions, filters in the time and frequency domains, or any numeric processing on the data.

Methods, systems, and devices for wireless communications are described. The described techniques provide for the described techniques provide for generating, by an encoding device, one or more entropy symbols, the length of which changes responsive to errors, stacking the entropy symbols into fixed intervals, and selecting a parity bit. The encoding device may divide entropy symbols that are longer than the fixed interval duration and stack the excess portions of the long entropy symbols with shorter entropy symbols in other intervals. The encoding device may transmit the stacked data packet according to the stacking. A decoding device may receive the data packet, identify the locations of the entropy symbols and the selected parity bit, check the parity of each entropy symbol, identify error bits based on the locations of the entropy symbols within multiple fixed intervals, and may correct error bits based on the stacked intervals, the parity bit, and an error mask.

A data encoding system includes a non-transitory memory, a processor, a digital-to-analog converter (DAC) and a transmitter. The non-transitory memory stores a predetermined file size threshold. The processor is in operable communication with the memory, and is configured to receive data. The processor detects a file size associated with the data. When the file size is below the predetermined file size threshold, the processor compresses the data using a variable length codeword (VLC) encoder. When the file size is not below the predetermined file size threshold, the processor compresses the data, using a hash table algorithm. The DAC is configured to receive a digital representation of the compressed data from the processor and convert the digital representation of the compressed data into an analog representation of the compressed data. The transmitter is coupled to the DAC and configured to transmit the analog representation of the compressed data.