A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

A delta sigma modulator includes two adders, an integrator stage, a reconfigurable local resonator, an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC). A first adder receives an analog input signal at an additive input, and the integrator stage receives an output from the first adder and generates an integrated signal. The reconfigurable local resonator receives the integrated signal and generates a resonator output signal. A second adder receives the resonator output signal, the integrated signal, and the input signal. The ADC receives an output from the second adder and generates a digital output signal which can be provided to other circuits. The DAC receives the digital output signal, and generates and provides a feedback signal to a subtractive input of the first adder. The reconfigurable local resonator acts as a resonator, but reconfigures to act as a low pass filter in response to overload conditions.

A delta sigma modulator includes two adders, an integrator stage, a reconfigurable local resonator, an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC). A first adder receives an analog input signal at an additive input, and the integrator stage receives an output from the first adder and generates an integrated signal. The reconfigurable local resonator receives the integrated signal and generates a resonator output signal. A second adder receives the resonator output signal, the integrated signal, and the input signal. The ADC receives an output from the second adder and generates a digital output signal which can be provided to other circuits. The DAC receives the digital output signal, and generates and provides a feedback signal to a subtractive input of the first adder. The reconfigurable local resonator acts as a resonator, but reconfigures to act as a low pass filter in response to overload conditions.

A delta-sigma modulator and a delta-sigma converter include an analog amplifying unit to amplify an analog signal and having at least a primary feedback coefficient, a quantizer to quantize an output signal of the analog amplifying unit, a DA converter to perform DA conversion on output of the quantizer and output a feedback signal, an adder-subtractor to input into the analog amplifying unit an analog signal obtained by subtracting the feedback signal from an analog signal input therein, a reset circuit to reset the analog amplifying unit at predetermined periods, and a control circuit to control the analog amplifying unit so that the analog amplifying unit operates as an integrator with the primary feedback coefficient of 1 until a predetermined period elapses after the reset circuit resets the analog amplifying unit and as an amplifier with the primary feedback coefficient of greater than one after the predetermined period has elapsed.

A delta-sigma modulator and a delta-sigma converter include an analog amplifying unit to amplify an analog signal and having at least a primary feedback coefficient, a quantizer to quantize an output signal of the analog amplifying unit, a DA converter to perform DA conversion on output of the quantizer and output a feedback signal, an adder-subtractor to input into the analog amplifying unit an analog signal obtained by subtracting the feedback signal from an analog signal input therein, a reset circuit to reset the analog amplifying unit at predetermined periods, and a control circuit to control the analog amplifying unit so that the analog amplifying unit operates as an integrator with the primary feedback coefficient of 1 until a predetermined period elapses after the reset circuit resets the analog amplifying unit and as an amplifier with the primary feedback coefficient of greater than one after the predetermined period has elapsed.