A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.

A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.

Integrator circuits comprising switched capacitors, non-switched capacitors, and an op amp. One embodiment is directed to an integrator circuit comprising an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output, a first sampling capacitor and a first feedback capacitor, and a first non-switched capacitor. The first feedback capacitor is coupled between the inverting input and the non-inverting output of the op amp, and the first non-switched capacitor is coupled between the negative integrator input and the inverting input of the op amp. During a sampling phase, a positive integrator input is coupled to the first sampling capacitor, and during an integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.

Integrator circuits comprising switched capacitors, non-switched capacitors, and an op amp. One embodiment is directed to an integrator circuit comprising an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output, a first sampling capacitor and a first feedback capacitor, and a first non-switched capacitor. The first feedback capacitor is coupled between the inverting input and the non-inverting output of the op amp, and the first non-switched capacitor is coupled between the negative integrator input and the inverting input of the op amp. During a sampling phase, a positive integrator input is coupled to the first sampling capacitor, and during an integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.

A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.

A method for measuring capacitance may include integrating charge with a charge integrator having a charge integrator input and output, filtering, with a loop filter having a loop filter input coupled to the charge integrator output and having a loop filter output, a first signal generated at the charge integrator output, quantizing, with quantizer having a quantizer input coupled to the loop filter output and a having quantizer output, a second signal generated at the loop filter output, processing, with a first feedback path having a first feedback path input coupled to the quantizer output and a first feedback path output coupled to the charge integrator input, a low-frequency spectrum of a quantizer output signal, and processing, with a second feedback path having a second feedback path input coupled to the quantizer output and a second feedback path output coupled downstream in a signal path of the apparatus relative to the charge integrator, a high-frequency spectrum of the quantizer output signal.

A delta-sigma modulation apparatus performs delta-sigma modulation on a first signal as an input signal and outputs a second signal; learns a parameter for a transmission path distortion model using the second signal and a third signal generated through a transmission path of the second signal; inputs the second signal to the transmission path distortion model and outputs a fourth signal that is an approximated value of a signal which is generated through at least part of the transmission path of the second signal, and performs the delta-sigma modulation on the first signal using the fourth signal and outputs the second signal.

A detector comprising: a filter arrangement configured to receive an output from a sigma-delta analogue to digital, SD-ADC, converter and generate a filtered output; a threshold comparison element configured to receive the filtered output and determine if signal content present in the filtered output is above or below a predetermined threshold, and wherein the detector is configured to, based on the determination of the threshold comparison element, output a flag signal indicative of a determination that the output of the SD-ADC is one of stable or unstable.