The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L error feedback modulator (EFM) stages, wherein the jth EFM stage is configured to receive as an input the sum of the error of the preceding EFM stage and a high amplitude dither signal derived from the error of the kth EFM stage, where 1≤j≤k≤L.

A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2.sup.nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency(fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2.sup.nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency (fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

A notch filter in a sigma-delta modulator loop filter increases SNR by limiting in-band quantization noise around a frequency to which the notch filter is precisely tuned. A tuning mode controller isolates the notch filter from other loop filter stages. A bias voltage is applied to the notch filter, causing it to resonate. Tuning mode switches insert the notch filter into a frequency-locked loop (“FLL”) circuit as a variable frequency oscillator component of the FLL. An ADC operational mode input signal is applied to the FLL as a reference signal. A tuning control component of the FLL adjusts a tunable feedback element in the notch filter to drive the FLL error signal to zero in order to precisely tune the notch filter to the center frequency of the ADC input signal. Tuning inputs to the tunable feedback element are then latched prior to re-inserting the notch filter into the modulator.

The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the jth stage is configured to receive as an input the sum of the error of the preceding stage and a high amplitude dither signal derived from the error of the kth stage, where 1≤j≤k≤L.

A correction method and a correction circuit for a sigma-delta modulator (SDM) are disclosed. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC), and the loop filter includes a resonator. The correction circuit includes a memory and a control circuit. The memory stores multiple program instructions. The control circuit executes the program instructions to correct the SDM. The correction procedure of the SDM includes the following steps: inputting a test signal to the SDM; obtaining a signal characteristic value of an output signal of the SDM; and adjusting the resonator according to the signal characteristic value.

An apparatus for a signal processor for Wide-Band Applications is provided. The signal processor includes a plurality of parallel branches. Each parallel branch includes a frequency shifter, a sigma-delta-modulator, and a filter. The output signal of each branch is combined via a signal recombiner. The signal processor is suitable for wide-band applications due to centering the zeros of the sigma-delta-modulator's noise transfer function and filter's noise transfer function at the frequency of the frequency shifter in the same branch of the signal processor. Centering these zeros at the frequency of the frequency shifter shapes the quantization noise added by the sigma-delta-modulator away from the input signal frequency to make it easier to remove the quantization noise. This wideband performance is also achieved due to the design of the embodiment's filters. The embodiments of this invention use filters with symmetric transition bands and a pass-band that is wide enough for use in wireless applications.

A correction method and a correction circuit for a sigma-delta modulator (SDM) are disclosed. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC), and the loop filter includes a resonator. The correction circuit includes a memory and a control circuit. The memory stores multiple program instructions. The control circuit executes the program instructions to correct the SDM. The correction procedure of the SDM includes the following steps: inputting a test signal to the SDM; obtaining a signal characteristic value of an output signal of the SDM; and adjusting the resonator according to the signal characteristic value.

The present disclosure relates to a modulator for a digital amplifier and a device comprising such a modulator and a digital amplifier. The modulator includes a pulse shaper and a control unit for controlling the pulse shaper to convert an input signal into a bit stream configured for a digital amplifier which encodes an amplitude value per clock of a carrier signal. The pulse shaper can represent a respective amplitude value of the input signal with different bit patterns. The control unit includes an assignment of the control commands to associated amplitude values resulting from amplification of the associated bit patterns with the digital amplifier is stored or at least is provided in that the control unit selects a control command per clock by means of the assignment and the amplitude value of the input signal and drives the pulse shaper accordingly.

Systems and methods for asynchronous data communication are disclosed. The system includes one or more peripheral devices, a processing device, and one or more communication channels. Each peripheral device includes a peripheral clock and a quantizer. The processing device is remotely located from each peripheral device and includes a processor clock that is asynchronous with at least one peripheral clock, an analog continuous time filter, and an analog-to-digital converter. The analog continuous time filter filters one or more quantized signals generated by the one or more peripheral devices to generate one or more filtered signals. The analog continuous time filter has a filter bandwidth corresponding to a signal bandwidth of one or more analog time varying signals represented by the one or more quantized signals. The analog-to-digital converter generates one or more converted signals by sampling the one or more filtered signals based on a processor clock signal.