Methods and apparatus, including computer program products, are provided for receivers. In one aspect there is provided an apparatus. The apparatus may include an in-phase sigma delta receiver coupled to a radio frequency input port providing at least a first carrier aggregation signal and a second carrier aggregation signal; and a quadrature phase sigma delta receiver coupled to the radio frequency input port providing at least the first carrier aggregation signal and the second aggregation signal, wherein the in-phase sigma delta receiver and the quadrature phase sigma delta receiver each include a resonator stage circuitry including at least one variable capacitor that varies notch frequencies to provide passbands for the first carrier aggregation signal and the second carrier aggregation signal. Related apparatus, systems, methods, and articles are also described.

A classifier system implementing an equivalent deep neural network (DNN) includes a weight block, classification block, row selector, and sensor array coupled with the weight block, classification block and row selector. The sensor array includes row lines, column lines, a data integration line, an integration start line, and multiple sensor cells corresponding to respective neurons in an input layer of the equivalent DNN. The sensor cells share a common terminal connected to the data integration line, the row lines are controlled by the row selector, and the column lines receive respective weight values from the weight block. The classification block includes a first integrator receiving a signal generated on the data integration line when the integration start line is selected, and a first thresholding unit receiving a signal from the first integrator. The first thresholding unit is coupled to second integrators and second thresholding units arranged in a two-dimensional matrix.

A delta-sigma modulator includes a first amplifier having an input, a feedback control input, and an output. The input is a first input of the delta-sigma modulator. The delta-sigma modulator further includes a first integrator and a first quantizer. The first integrator has an input and an output. The output of the first amplifier is coupled to the input of the first integrator. The first quantizer has an input and an output. The output of the first quantizer is coupled to the feedback control input of the first amplifier.

A delta-sigma modulator includes a first amplifier having an input, a feedback control input, and an output. The input is a first input of the delta-sigma modulator. The delta-sigma modulator further includes a first integrator and a first quantizer. The first integrator has an input and an output. The output of the first amplifier is coupled to the input of the first integrator. The first quantizer has an input and an output. The output of the first quantizer is coupled to the feedback control input of the first amplifier.

An integrator circuit (10) for use in a sigma-delta modulator (1) comprises a differential operational amplifier (130) with a first input node (E130a) and a second input node (E130b). The first input node (E130a) of the differential operational amplifier (130) is connected to a first current path (101) and the second input node (E130b) of the differential operational amplifier (130) is connected to a second current path (102). A first controllable switch (111) is arranged between the second input node (E130b) of the differential operational amplifier (130) and the first current path (101). A second controllable switch (112) is arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102). A third controllable switch (113) is arranged between a reference potential (RP) and the first current path (101). A fourth controllable switch (114) is arranged between the reference potential (RP) and the second current path (102).

An integrator circuit (10) for use in a sigma-delta modulator (1) comprises a differential operational amplifier (130) with a first input node (E130a) and a second input node (E130b). The first input node (E130a) of the differential operational amplifier (130) is connected to a first current path (101) and the second input node (E130b) of the differential operational amplifier (130) is connected to a second current path (102). A first controllable switch (111) is arranged between the second input node (E130b) of the differential operational amplifier (130) and the first current path (101). A second controllable switch (112) is arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102). A third controllable switch (113) is arranged between a reference potential (RP) and the first current path (101). A fourth controllable switch (114) is arranged between the reference potential (RP) and the second current path (102).

A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.

A loop-filter comprising: a first-integrator, and one or more further-integrators. The first-integrator is an active-RC integrator, and comprises a first-integrator-input-terminal configured to receive: (i) an input-signal, and (ii) a feedback-signal; a first-integrator-first-output-terminal configured to provide a first-integrator-first-output-signal; and one or more first-integrator-further-output-terminals. Each of the one or more further-integrators is a Gm-C integrator, and they are connected in series between the first-integrator-first-output-terminal and a loop-filter-output-terminal. For a first further-integrator in the series, the further-integrator-input-terminal is configured to receive the first-integrator-first-output-signal. For any subsequent further-integrators in the series, the further-integrator-input-terminal is configured to receive: (i) the further-integrator-output-signal from the preceding further-integrator in the series; and (ii) one of the first-integrator-further-output-signals.

A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.

A classifier system implementing an equivalent deep neural network (DNN) includes a weight block, classification block, row selector, and sensor array coupled with the weight block, classification block and row selector. The sensor array includes row lines, column lines, a data integration line, an integration start line, and multiple sensor cells corresponding to respective neurons in an input layer of the equivalent DNN. The sensor cells share a common terminal connected to the data integration line, the row lines are controlled by the row selector, and the column lines receive respective weight values from the weight block. The classification block includes a first integrator receiving a signal generated on the data integration line when the integration start line is selected, and a first thresholding unit receiving a signal from the first integrator. The first thresholding unit is coupled to second integrators and second thresholding units arranged in a two-dimensional matrix.