A delta-sigma modulator may include a loop filter, a quantizer, an input gain element having a programmable input gain and coupled between an input of the delta-sigma modulator and an input of the loop filter, a feedforward gain element having a programmable feedforward gain and coupled between the input of the delta-sigma modulator and an output of the loop filter, and a quantizer gain element having a quantizer gain and coupled between the output of the loop filter and an input of the quantizer. The programmable input gain is controlled in order to control a variable gain of the delta-sigma modulator. The programmable feedforward gain is controlled to be equal to the ratio of the programmable input gain and the quantizer gain such that the delta-sigma modulator has a fixed phase response.

Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2.sup.nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency(fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.

A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

A current to digital converter circuit has an integrator amplifier with an input adapted to receive a current signal and an output adapted to provide a voltage signal as a function of an integration of the current signal, a quantizer circuit with an input which is coupled to the output of the integrator amplifier and with an output adapted to provide a binary result signal as a function of a comparison of the voltage signal with at least a first reference voltage signal, a digital-to-analog converter circuit which is coupled in a switchable manner as a function of the binary result signal to the input of the integrator amplifier, and a controlled current source which is coupled to the output of the integrator amplifier via a first switch which is controlled as a function of the binary result signal such that an auxiliary current is supplied to the output of the integrator amplifier.

A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2.sup.nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency (fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

An excess loop delay compensation (ELDC) technique for use with a successive approximation register (SAR) based quantizer in a continuous time delta-sigma ADC is described. The techniques can efficiently program and calibrate the ELD gain in ELD compensation SAR quantizers. An ELDC circuit can include a charge pump having a digitally programmable capacitance to adjust a gain, such as the gain of the ELDC digital-to-analog converter (DAC) or the gain of the SAR DAC.

A filter system includes: a first mixer, converting an input signal into a first signal according to a reference frequency signal, wherein the reference frequency signal corresponding to a target frequency band; an analog-to-digital converter, coupled to the first mixer, converting the first signal into a first digital signal; a digital filter, coupled to the analog-to-digital converter, filtering the first digital signal according to a first frequency band and generating a second digital signal, wherein the first frequency band corresponding to the first signal; a digital-to-analog converter coupled to the digital filter, converting the second digital signal into a second signal; and a second mixer, coupled to the digital-to-analog converter, converting the second signal into an output signal according to the reference frequency signal, wherein the output signal corresponds to the input signal filtered by the target frequency band.