A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

Technologies directed to improving power for wireless transceivers are described. One method determines, in a first mode, a first value associated with a wireless link and a second values associated with the wireless link, the first value being indicative of a first metric and the second value being indicative of a second metric different from the first metric. The first value and the second value collectively indicate a category of channel quality for the wireless link. The method determines that the wireless device can operate in a second mode for subsequent data based on the category of channel quality, wherein in the second mode the wireless device consumes less power than in the first power mode. The method receives, in the second mode, second data over the wireless link.

A receiver includes a switch network, a mixer, and an IQ mismatch (IQMM) estimation circuit. The switch network is adapted to be coupled to an output of a transmitter. The switch network is configured to selectably swap complementary signals of a differential pair. The mixer is coupled to the switch network and is configured to down-convert an output signal of the switch network. The IQ IQMM estimation circuit is coupled to the mixer, and is configured to estimate an IQMM of the transmitter based on an output signal of the mixer.

A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.

A transmitter circuit includes at least one transmitting signal processing device, a compensation device and a compensation value calibration device. The compensation device generates a first compensated input signal and a second compensated input signal by respectively processing input signals according to a first compensation value and a second compensation value. The transmitting signal processing device generates a first output signal and a second output signal by processing the first compensated input signal and the second compensated input signal. The compensation value calibration device receives the first output signal and the second output signal as a first feedback signal and a second feedback signal, respectively, and includes a digital signal processor. The digital signal processor determines a calibrated compensation value according to power of the first feedback signal and the second feedback signal at a predetermined frequency and the first compensation value and the second compensation value.

A transmitter circuit includes at least one transmitting signal processing device, a compensation device and a compensation value calibration device. The compensation device generates a first compensated input signal and a second compensated input signal by respectively processing input signals according to a first compensation value and a second compensation value. The transmitting signal processing device generates a first output signal and a second output signal by processing the first compensated input signal and the second compensated input signal. The compensation value calibration device receives the first output signal and the second output signal as a first feedback signal and a second feedback signal, respectively, and includes a digital signal processor. The digital signal processor determines a calibrated compensation value according to power of the first feedback signal and the second feedback signal at a predetermined frequency and the first compensation value and the second compensation value.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

A test apparatus includes a device under test (DUT) configured to exchange data using a serial interface protocol and a test controller configured to receive a binary vector corresponding to a physical layer of the serial interface protocol from an external device and to buffer and transmit the received binary vector to the DUT.

A receiver includes a switch network, a mixer, and an IQ mismatch (IQMM) estimation circuit. The switch network is adapted to be coupled to an output of a transmitter. The switch network is configured to selectably swap complementary signals of a differential pair. The mixer is coupled to the switch network and is configured to down-convert an output signal of the switch network. The IQ IQMM estimation circuit is coupled to the mixer, and is configured to estimate an IQMM of the transmitter based on an output signal of the mixer.