H04B2001/307

Hybrid Distortion Suppression System and Method
20230231585 · 2023-07-20 ·

A method for reducing distortions of a radio frequency (RF) system includes configuring a plurality of mixers to convert between a plurality of phase signals and a plurality of RF signals, configuring a first mixer of the plurality of mixers to operate in a six-phase operating mode to reduce the distortions of the RF system, and configuring a second mixer of the plurality of mixers to operate in a three-phase operating mode to reduce power consumption of the RF system.

Circuits for intermediate-frequency-filterless, double-conversion receivers

Circuits for a receiver, comprising: M first mixers that each receive an input signal, that are each clocked by a different phase of a first common clock frequency, and that each provide an output, wherein M is a count of the first mixers; and M sets of N second mixers, wherein N is a count of the second mixers in each of the M sets, wherein each second mixer in each set of N second mixers receives as an input the output of a corresponding one of the M first mixers, wherein each of the N second mixers in each of the M sets are clocked by a different phase of a second common clock frequency, and wherein each of the second mixers has an output.

Transceiver with time domain IQMM estimation
11695442 · 2023-07-04 · ·

A receiver includes a switch network, a mixer, and an IQ mismatch (IQMM) estimation circuit. The switch network is adapted to be coupled to an output of a transmitter. The switch network is configured to selectably swap complementary signals of a differential pair. The mixer is coupled to the switch network and is configured to down-convert an output signal of the switch network. The IQ IQMM estimation circuit is coupled to the mixer, and is configured to estimate an IQMM of the transmitter based on an output signal of the mixer.

RADIO FREQUENCY RECEIVER CIRCUIT

A radio frequency, RF, receiver circuit is configured to simultaneously monitor a two or more different RF frequencies. The RF receiver circuit uses a sub-sampler to sub-sample an RF signal that is at any of the monitored RF frequencies, and the sub-sampled signal is then demodulated and a digital code that was encoded in the RF signal is recovered. The RF receiver circuit may be particularly low power, in part owing to using the same sub-sampler for each of the two or more monitored RF frequencies, and not relying on superheterodyning. Furthermore, monitoring two or more different RF frequencies simultaneously means that signals received on the monitored RF frequencies may be acted on very quickly. These characteristics make the RF receiver circuit particularly suitable for use in low-power wake-up receivers, such as Bluetooth Low Energy (BLE) wake-up receivers.

RADIO COMMUNICATION CIRCUIT WITH RADIO FREQUENCY QUADRATURE GENERATION
20220407544 · 2022-12-22 ·

Radio communication circuits, radio transmitters, and methods are provided in this disclosure. The radio communication circuit may include a modulator configured to provide a first modulated signal including a carrier signal at a carrier frequency, and a second modulated signal including the carrier signal at the carrier frequency. The radio communication circuit may further include a phase shift generator configured to receive a first signal based on the first modulated signal and a second signal based on the second modulated signal. The phase shift generator of the radio communication circuit may further be configured to provide a predefined phase difference between the first signal and the second signal.

Integrated high speed wireless transceiver
11515901 · 2022-11-29 · ·

A direct digital radio having a high-speed RF front end in communication with an antenna, and a radio subsystem that can be configured to form a programmable multi-standard transceiver system. The high-speed RF front including RF inputs configured to receive a plurality of radio frequencies (e.g., frequencies between 400 MHz to 7.2 GHz, millimeter wave frequency signals, etc.) and wideband low noise amplifiers provides amplified signals to RF data converters, analog interfaces, digital interfaces, component interfaces, etc. The programmable multi-standard transceiver is operable in frequencies compatible with multiple networks such as private LTE and 5G networks as well as other wireless IoT standards and WiFi in multi-standard network access equipment. The programmable multi-standard transceiver can greatly reduce complexity for the baseband processing, lower the cost of the overall transceiver system, reduce power consumption, and at the same time, benefit from improvements on the digital functions through integration.

CONFIGURABLE HARMONIC REJECTION MIXER (HRM)

This disclosure provides systems, methods, and devices for wireless communication that support reconfiguring degeneration components in a converged RF transceiver supporting carrier aggregation across sub-6 GHz frequency bands and mmWave frequency bands. In a first aspect, an apparatus includes an input port configured to receive a mixer input signal; a first mixer forming at least a portion of an HRM mixer and coupled to the input port; a first configurable degeneration component of a first processing path coupled between the input port and the first mixer; and a controller coupled to the first degeneration component, wherein the controller is configured to control a first aspect of a first degeneration component. Other aspects and features are also claimed and described.

WIRELESS SIGNAL PROCESSING CIRCUIT AND WIRELESS DEVICE
20220345160 · 2022-10-27 · ·

A wireless signal processing circuit includes plural phase switchers, plural variable amplifiers and plural mixers. The plural phase switchers are provided on each of plural paths along which all in-phase signal and a quadrature signal are distributed. The plural phase switchers rotate the phases of the signals by signal phase rotation amounts according to a transmission direction of a transmission signal. The plural variable amplifiers alter amplitudes of input signals or output signals of the corresponding phase switchers in accordance with the transmission direction of the transmission signal. The plural mixers up-convert frequencies of the signals processed by the corresponding phase switchers and variable amplifiers.

Semiconductor chip with local oscillator buffer reused for loop-back test and associated loop-back test method

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.

INTEGRATED HIGH SPEED WIRELESS TRANSCEIVER
20230155615 · 2023-05-18 · ·

A direct digital radio having a high-speed RF front end in communication with an antenna, and a radio subsystem that can be configured to form a programmable multi-standard transceiver system. The high-speed RF front including RF inputs configured to receive a plurality of radio frequencies (e.g., frequencies between 400 MHz to 7.2 GHz, millimeter wave frequency signals, etc.) and wideband low noise amplifiers provides amplified signals to RF data converters, analog interfaces, digital interfaces, component interfaces, etc. The programmable multi-standard transceiver is operable in frequencies compatible with multiple networks such as private LTE and 5G networks as well as other wireless IoT standards and WiFi in multi-standard network access equipment. The programmable multi-standard transceiver can greatly reduce complexity for the baseband processing, lower the cost of the overall transceiver system, reduce power consumption, and at the same time, benefit from improvements on the digital functions through integration.