Systems and methods for implementing a software emulation of a clock calibrated by the software based on sampling a hardware clock.

A sensor may determine a sampling pattern based on a group of synchronization signals received by the sensor. The sampling pattern may identify an expected time for receiving an upcoming synchronization signal. The sensor may trigger, based on the sampling pattern, a performance of a sensor operation associated with the upcoming synchronization signal. The performance of the sensor operation may be triggered before the upcoming synchronization signal is received.

An EtherCAT device is disclosed. The EtherCAT device comprises a data input port to receive a signal representing data, the signal representing one of a plurality of possible logical values; and a degradation calculation circuit. The degradation calculation circuit is to read, demodulate, and convert the received signal into a digital domain representation; process the digital domain representation into slices, where the value of the received signal at a respective time is represented in a respective one of the slices; determine differences between the respective slices and reference slices; identify an intended logical value of the received signal responsive to the determined differences; determine a quantification of error at the respective time responsive to the identified logical value and the determined differences; and determine a signal quality index responsive to the determined quantification of error.

There is provided a GNSS independent method for asymmetry delay error compensation to minimize a time difference bias when using two-way time transfer in a communication network. The method includes establishing a bidirectional virtual path comprising at least one link path, LP1-LP4, over the network for communication between a first node A and a second node B by sending a bidirectional data stream over the virtual path and utilizing previously stored link profiles associated with a delay correction factor or a calibrated virtual path or a stable local clock in holdover mode to provide new delay correction factor to minimize a time difference bias in the local time in the second node.

An interface conversion apparatus includes processing circuitry. The processing circuitry measures communication quality inside the mobile communication system. The processing circuitry refers to evaluation index information specifying, for each communication group, an allowable range of variation in the measurement result of the communication quality and a fluctuation adjustment time, and determines the communication group in which a variation in the measurement result of the communication quality obtained from history information including a measurement result falls within the allowable range for each piece of identification information included in the packet. The processing circuitry selects the communication group of the packet received from the identification information of the packet received, based on a correspondence relationship between the communication group determined and the identification information of the packet. The processing circuitry controls the packet received for each communication group, using the fluctuation adjustment time in the evaluation index information corresponding to the communication group determined.

Two or more modules communicate over a common control network including receiving by a message packet having data defined by a signal level at defined bit quanta of a bit, the defined bit quanta being less than every bit quanta of a bit, and the communication device samples bit quanta other than the defined bit quanta. The module receives signal disturbances and decodes the signal disturbances as having a value different from an expected value of the certain bit. In another form, the module uses a first counter based on a clock local to the communication device and a second counter having a higher sampling rate than the first counter. Here, the module receives over the control network a synchronizing portion of a message and counts clock ticks of the second counter over a portion of the message to determine a clock rate for a module that transmitted the message.

A communication link initialization method includes that a master node sends a first information frame to a slave node. The first information frame includes first synchronization information. The slave node implements synchronization with the master node based on the first synchronization information. The slave node sends a second information frame to the master node. The second information frame includes second synchronization information. The master node implements synchronization with the slave node based on the second synchronization information. The master node sends a third information frame to the slave node. The third information frame is used to indicate a first training information frame. The slave node trains a link between the master node and the slave node based on the third information frame. The slave node sends a fourth information frame to the master node.

A method for synchronizing a network device includes: receiving, by the network device, a first SSM and a second SSM, where the first SSM carries a first SSM code for indicating a quality level of a first clock source and a first eSSM code for indicating the quality level of the first clock source, and the second SSM carries a second SSM code for indicating a quality level of a second clock source and a second eSSM code for indicating the quality level of the second clock source. When a value of the first SSM code is less than a value of the second SSM code, the network device calibrates a frequency of the network device based on a timing signal of the first clock source.

A communication method implemented by a terminal device includes detecting whether a clock source declaration from a user plane network element is received within a first duration, and when the terminal device does not receive the clock source declaration from the user plane network element within the first duration, sending a clock source declaration from a remote device to the user plane network element. According to the method, when the terminal device does not receive the clock source declaration from the user plane network element within the first duration, this indicates that the user plane network element cannot receive a clock source declaration from another terminal device. Accordingly, the clock source declaration of the remote device is sent to the user plane network element.

Techniques that provide link auto-negotiation between a radio equipment controller (REC) and a radio equipment (RE) are described herein. In one embodiment, a method includes performing, by a proxy master, a Common Public Radio Interface (CPRI) Layer 1 (L1) link auto-negotiation with a RE to achieve a L1 synchronization between the proxy master and the RE at a link bit rate; communicating the link bit rate from the proxy master to a proxy slave; performing, by the proxy slave, a CPRI L1 link auto-negotiation with a REC to determine whether a L1 synchronization between the proxy slave and the REC is achieved, wherein if the L1 synchronization is achieved, the link bit rate is a common matching link bit rate achieved; and upon the common matching link bit rate being achieved, establishing a CPRI link between the REC and the RE using the common matching link bit rate.