The invention relates to a method for providing a fault-tolerant global time via a time server in a distributed real-time computer system, wherein the time server comprises four components which are connected to one another via a bi-directional communication channel. At a priori defined periodic, internal synchronization times, each of the four components transmits an internal synchronization message, which is simultaneously transmitted to the other three components, from which each internal computer of a component determines a correction term for the tick counter contained in its component and corrects the reading of the local tick counter by this correction term.

The invention relates to a method for providing a fault-tolerant global time and for the fault-tolerant transport of time-controlled messages in a distributed real-time computer system which comprises external computers and a fault-tolerant message distribution unit, FTMDU. The FTMDU comprises at least four components which supply the global time to the external computers by means of periodic external synchronization messages, wherein the external computers each set their local clock to the received global time, wherein each external sender of a time-controlled message transmits two message copies of the message to be sent via two different communication channels to two different components of the FTMDU at periodic sending times defined a priori in timetables, wherein these two message copies are delivered within the FTMDU via two independent communication paths to those two components of the FTMDU which are connected to an external receiver of the message via communication channels.

There is provided a method in a communication network system 100 of e.g. IP type for live distribution of media content capable of node-to-node time-transfer between nodes in the network system. The media content is sent as a data stream DS.sub.x via respective communication links over a network 200. The method comprises transferring local clock signal between nodes and based on received local clock signals determining a unidirectional delay between the nodes. The traffic between the nodes is then based on the determined unidirectional delay.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

A network system includes a synchronous master device to output a cooperative-operation timing signal in a cooperative-operation cycle, a time master station connected to a network, and a time slave station connected to the network. The time master station includes a master clock to count a time, and a master generation unit to generate master cooperative-operation-time information on the basis of the cooperative-operation timing signal and the time counted by the master clock. The time slave station includes a slave clock to count a time, and a slave generation unit to generate slave cooperative-operation-time information on the basis of the master cooperative-operation-time information and the time counted by the slave clock.

The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

Systems and methods are disclosed herein for syntonizing machines in a network. A coordinator accesses probe records for probes transmitted at different times between pairs of machines in the mesh network. For different pairs of machines, the coordinator estimates the drift between the pair of machines based on the transit times of probes transmitted between the pair of machines as indicated by the probe records. For different loops of at least three machines in the mesh network, the coordinator calculates a loop drift error based on a sum of the estimated drifts between pairs of machines around the loop and adjusts the estimated absolute drifts of the machines based on the loop drift errors. Here, the absolute drift is defined relative to a drift of a reference machine.

A method and a first device (110A) for synchronizing a first clock in the first device (110A) with a second clock in a second device (110B). The first device (110A) estimates 5 (A430) a relative clock phase offset, based on a sequence of round trip times, RTTs, of precision time protocol, PTP, messages which are exchanged between the first and second devices (110A, 110B). The estimated relative clock phase offset is a time difference between a time of arrival of a first arrived PTP message among the PTP messages and a direct subsequent clock cycle. The first device (110A) further determines 10 (A450) a clock value of the first clock, based on the estimated relative clock phase offset, to synchronize the first clock with the second clock.