Patent classifications
H04J3/0682
TIME SYNCHRONIZATION METHOD USING 5G REFERENCE TIME DISTRIBUTION AND NETWORK ENTITY PERFORMING THE SAME
Provided are a time synchronization method using 5G reference time distribution and a network entity performing the same. The time synchronization method may include receiving, by a time sensitive communication time synchronization function (TSCTSF), a 5G reference time distribution request including time synchronization parameter values from an application function (AF); performing, by the TSCTSF, policy modification; and transmitting, by the TSCTSF, a setting of the 5G reference time distribution to the AF.
Quantum secure network clock synchronization
A multi-node, quantum communication network for providing quantum-secure time transfer with Damon attack detection is described. The network includes three or more nodes connected via authenticated communication channels forming a closed loop. By determining differences between the local times at as well as the time durations required for photons to travel between the three or more nodes, the network detects a Damon attack, if present. For example, the network imposes a closed loop condition to detect the Damon attack. The network can also use the local time differences and time durations for photon travel between nodes to synchronize the local clocks at the three or more nodes of the network.
Synchronization mechanism for high speed sensor interface
A sensor may determine a sampling pattern based on a group of synchronization signals received by the sensor. The sampling pattern may identify an expected time for receiving an upcoming synchronization signal. The sensor may trigger, based on the sampling pattern, a performance of a sensor operation associated with the upcoming synchronization signal. The performance of the sensor operation may be triggered before the upcoming synchronization signal is received.
METHOD, A COMPUTER PROGRAM PRODUCT, AND A CARRIER FOR INDICATING ONE-WAY LATENCY IN A DATA NETWORK
Disclosed herein is a method, a computer program product, and a carrier for indicating one-way latency in a data network (N) between a first node (A) and a second node (B), wherein the data network (N) lacks continuous clock synchronization, comprising: a pre-synchronisation step, a measuring step, a post-synchronisation step, an interpolation step, and generating a latency profile. The present invention also relates to a computer program product incorporating the method, a carrier comprising the computer program product, and a method for indicating server functionality based on the first aspect.
A METHOD FOR TIME SYNCHRONIZATION OF DEVICES IN A CONTROL NETWORK
The present invention provides a method for time synchronizing one or more devices in a control network using a first device. The method comprises selecting a first device from information of the topology of the control network. The method further comprises sending a first set of packets to the second device, receiving a first set of delay requests in response to the first set of packets, and sending a first set of delay responses in response to the first set of delay requests. The method further comprises, determining a first set of forward times and first set of backward times. The method further comprises, determining a first minimum forward time and a first minimum backward time. Further the method comprises determining a first correction factor. The method also comprises, applying the first correction factor to a clock provided at the second device and storing the first correction factor.
SYSTEM AND METHOD OF SYNCHRONIZING A DISTRIBUTED CLOCK IN A PACKET-COMPATIBLE NETWORK
There are provided a clock node, a controller, a method of operating the clock node and a method of operating the controller in a time distribution network (TDN) comprising the controller being in data communication with the clock nodes via a control path. The method of operating the clock node comprises: sending, from the clock node via the control path to the controller, a first timestamp-related data; receiving, by the clock node via the control path from the controller, clock-recovery control data generated by the controller using the first timestamp-related data received from the clock node; processing the received clock-recovery control data to extract data usable for phase and frequency recovery; and using the extracted data to steer frequency and phase characterizing the clock node.
DETERMINISTIC CALIBRATED SYNCHRONIZED NETWORK INTERLINK ACCESS
Technologies for calibrated network interlink access. In some embodiments, a system can calculate a first communication latency of a first link between a first processing element in a first switch and a second processing element in a second switch, and a second communication latency associated with a second link between the first processing element and a third processing element in a third switch. The system can determine a delta between the first communication latency and the second communication latency, and whether respective clock rates of the first switch, second switch, and third switch have a clock rate variation, to yield a clock rate variation determination. Based on the delta and clock rate variation determination, the system can determine an offset value for synchronizing the first communication latency and second communication latency. Based on the offset value, the system can calibrate traffic over the first link and/or the second link.
High accuracy time stamping for multi-lane ports
In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.
METHOD FOR SECURING THE TIME SYNCHRONIZATION OF AN ETHERNET ON-BOARD NETWORK
A method for securing the time synchronization of an Ethernet on-board network of a motor vehicle, by: determining a delay time of a first signal on a first connecting path between a first control unit of the network and a second control unit of the network; determining a maximum speed of the first connecting path on the basis of the delay time; and determining a type of a transmission medium of the first connecting path on the basis of the maximum speed. The determination of the delay time of a first signal, the determination of the maximum speed of the first connecting path, and the determination of the type of a transmission medium of the first connecting path result in an entropy source being formed that is used to ascertain at least one dynamic key for the connecting path to encrypt a time synchronization message for the connecting path.
Clock error-bound tracker
In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.