The invention relates to a method for providing a fault-tolerant global time via a time server in a distributed real-time computer system, wherein the time server comprises four components which are connected to one another via a bi-directional communication channel. At a priori defined periodic, internal synchronization times, each of the four components transmits an internal synchronization message, which is simultaneously transmitted to the other three components, from which each internal computer of a component determines a correction term for the tick counter contained in its component and corrects the reading of the local tick counter by this correction term.

A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

A system can, in response to determining to capture bio telemetry data associated with client devices, synchronize respective second clock times of respective client devices with a first clock time maintained by a network time protocol server, wherein the respective client devices are configured to capture the bio telemetry data of respective users associated with the client devices, wherein the respective users are associated with respective user accounts. The system can synchronize the bio telemetry data of the respective users based the respective second clock times.

The present application provides a time synchronization method and an electronic device. The method includes sending a clock synchronization signal and first real time clock (RTC) information separately; and the clock synchronization signal is configured to measure a delay between a first module and at least one second module, the delay is used for phase compensation performed on the clock synchronization signal received at the side of the at least one second module, and the clock synchronization signal after being subjected to the phase compensation is configured to trigger the at least one second module to update local second RTC information to the first RTC information.

A method for timestamping and synchronization with high-accuracy timestamps in low-power sensor systems is provided. The method is performed by a device and includes: receiving, by a sensor hub of the device, an interrupt signal from a sensor and performing an interrupt service routine (ISR) to obtain an interrupt timestamp obtained by a latch, wherein the interrupt timestamp is obtained from an always-running unified time reference; obtaining, by the sensor hub, sensor data from the sensor; predicting, by the sensor hub, a prediction timestamp based on an amount of sensor data and the interrupt timestamp by using a filtering algorithm; and correcting, by the sensor hub, a timestamp of each sensor data based on the prediction timestamp.

A system is provided that includes a first electronic device, multiple second electronic devices coupled to the first electronic device via respective interfaces, and a clock generator coupled to the second electronic devices and configured to generate and provide a clock signal to each of the second electronic devices for clocking operation of the second electronic devices. The clock signal is a gapped clock signal having at least one gap created by the clock generator removing one or more clock pulses based on a synchronization signal, and the second electronic devices are configured to synchronize data transmission between the second electronic devices and the first electronic device via the interfaces using the at least one gap in the gapped clock signal to align the data transmission.

A clock delay detection method and apparats, a clock delay compensation method and apparatus, a terminal, and a readable storage medium. The clock delay detection method comprises: transmitting a first synchronization clock to a clock module to be detected by means of a first physical link (S101); receiving a feedback clock transmitted by said clock module by means of a second physical link and adjusted according to a phase of the first synchronization clock (S102); and thus determining the delay of said clock module according to the feedback clock, a self-return clock, a delay parameter corresponding to the first physical link, and a delay parameter corresponding to the second physical link (S103).

Methods, systems, and devices for wireless communications are described. A first device node, such as an end station or a user equipment (UE) associated with the end station, may receive, from a controller node of a time-sensitive network (TSN), a configuration for communicating over the TSN. The TSN may include a plurality of nodes that are synchronized according to a common synchronization configuration and that are configured for transmitting messages between the controller node and the first device node within a latency threshold condition configured for the TSN. The first device node may identifying data to transmit to a second device node of the plurality of nodes and may communicating with the second device node via a sidelink connection associated with the wireless radio access network.

A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal. The one or more second units (104) each comprise: a slave time block (141) configured to: determine a slave-time-signal (142) for the second unit (104) based on the master-timing-reference-signal; determine one or more second-timing-values based on the slave-time-signal; determine an adjustment-time based on the first-unit-timing-signal received from the first unit (102) and the second-timing-values; and adjust the slave-time-signal based on the adjustment-time.

An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.