A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

A frequency converter has a control unit. The control unit has: a serial control unit interface, a control unit clock pulse generator for generating a control unit clock pulse, wherein data are transmitted via the serial control unit interface depending on the control unit clock pulse, and a control unit processor which is designed to define at least one control parameter depending on at least one actual value. The frequency converter furthermore has a power unit which has a data connection to the control unit and has: a number of power semiconductors, a power unit clock pulse generator for generating an adjustable power unit clock pulse, a serial power unit interface which is connectable to the control unit interface in order to set up a data connection, a clock pulse generator adjustment unit which has a signal connection to the power unit interface and which is designed to adjust the power unit clock pulse depending on signals which are received by the power unit on the power unit interface, a power unit processor which is designed to control the power semiconductors depending on the control parameter and the power unit clock pulse, and at least one sensor unit which is designed to determine the at least one actual value, wherein the control unit is designed to transmit the at least one control parameter via the control unit interface to the power unit, and wherein the power unit is designed to transmit the at least one actual value via the power unit interface to the control unit.

A cell processing method and apparatus are provided. The method includes: obtaining, by a first sending end, a first timestamp compensation time; adding, by the first sending end, the first timestamp compensation time to a first timestamp carried in a first cell, where the first timestamp is a sending time of the first cell; and sending, by the first sending end to a receiving end, the first cell that is added with the first timestamp compensation time, so that the receiving end forwards the first cell according to the first timestamp that is added with the first timestamp compensation time. In the present invention, a first timestamp compensation time is added to a first timestamp carried in a first cell, which improves cell forwarding efficiency of the receiving end and prevents the occurrence of cell accumulation in a link.

A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

Certain features relate to improving the link-fault tolerance in a distributed antenna system (DAS) by utilizing a series of synchronous communication frames. A receiving remote unit or a head-end unit in the DAS can predict the start of incoming communication frames based on frame information extracted from previously received communication frames. For example, a remote unit can be configured to receive one or more communication frames, each of the one or more communication frames including a start-of-frame field. After a period of time corresponding to the frame repetition rate, the remote unit can search for an additional start-of-frame field, indicating the receipt of the next communication frame. The remote unit can extract the payload data from the next communication frame based on the predicted value for the additional start-of-frame field.

A method for evaluating signal data includes a bus signal channel supplying the signal data, a reference channel supplying reference signal values, which form the basis of the signal data, and a computer performing a signal interpretation based on an interpretable portion of the signal data and on the reference signal values, and reconstructing a signal based on the interpretation.

This invention is related to an Express Traversal (EXTRA) Network on Chip (NoC) comprising a number of EXTRA routers. The EXTRA NoC comprises a Buffer Write and Route Computation (BW/RC) pipeline, a Switch Allocation-Local (SA-L) pipeline, a Setup Request (SR) pipeline, a Switch Allocation-Global (SA-G) pipeline, and a Switch Traversal and Link Traversal (ST/LT) pipeline. The BW/RC pipeline is configured to write an incoming flit to an input buffer(s) of a start EXTRA router and compute the route for the incoming head flit by selecting an output port to depart from the start EXTRA router. The SA-L pipeline is configured to arbitrate the start EXTRA router to choose an input port and an output port for a winning flit. The SR pipeline is configured to handle the transmission of a number of SR signals from the start EXTRA router to downstream EXTRA routers.

A frequency converter control unit has: a serial control unit interface, a control unit clock pulse generator for generating a control unit clock pulse, and a control unit processor which is designed to define a control parameter depending on an actual value. A power unit has a data connection to the control unit and has several power semiconductors, a power unit clock pulse generator for generating an adjustable power unit clock pulse, a serial power unit interface, a clock pulse generator adjustment unit which has a signal connection to the power unit interface and which adjusts the power unit clock pulse depending on signals received by the power unit on the power unit interface, a power unit processor which controls the power semiconductors depending on the control parameter and the power unit clock pulse, and a sensor unit that determines the actual value. The control unit transmits the control parameter via the control unit interface to the power unit. The power unit transmits the actual value via the power unit interface to the control unit.

A device that includes a plurality of transceivers configurable to simultaneously operate with a combination of bonded and unbonded transceivers. A first transceiver of the plurality of transceivers is operable at a first data rate, and a second transceiver of the plurality of transceivers is simultaneously operable at a second data rate that is different than the first data rate. The first and second transceivers are operable as bonded transceivers and wherein a third transceiver, of the plurality of transceivers, is simultaneously operable at a third data rate and the third transceiver is not bonded with any other transceiver.

A physical layer circuit of a receiver, a clock recovery circuit and a calibration method of frequency offset are provided. The physical layer circuit includes an equalizer and a clock recovery circuit. The equalizer generates an equalized sampling signal corresponding to a sampling clock signal. The clock recovery circuit includes a phase detector, a loop filter, a free wheel circuit, an output circuit and a controller. The phase detector calculates phase differences according to the equalized sampling signal. The loop filter generates loop pulses according to the phase differences. The free wheel circuit generates free wheel pulses. The output circuit receives the loop pulses and the free wheel pulses and generates corresponding phase-shifting pulses for adjusting the sampling clock signal. The controller calculates an accumulative correction offset according to the phase-shifting pulses, and the free wheel circuit periodically generates the free wheel pulses accordingly.