An adaptive line driver circuit configured to transmit a signal over a wired link includes a delay-locked loop (DLL) circuit, which includes a phase detector (PD) circuit, charge pump (CP) circuit, and voltage-controlled delay line (VCDL) circuit operatively coupled together. The delay-locked loop circuit provides pre-emphasis and feed-forward equalization of the signal. The delay locked loop circuit also provides a user-configurable parameter including at least one of pre-data tap amplitude, data tap amplitude, post-data tap amplitude, pre-data tap duration, post-data tap duration, pre-data tap quantity, and post-data tap quantity. The adaptive line driver circuit further includes a source-series terminated (SST) driver circuit operatively coupled to the delay-locked loop circuit.

A digital signal processing (DSP) device includes a first fitter to equalize channel dispersion associated with signal transmission through a medium, a second filter to cancel channel reflections, and a third filter to at least reduce noise. The DSP device is a receiver DSP of the SERDES.

A digital signal processing (DSP) device includes a first fitter to equalize channel dispersion associated with signal transmission through a medium, a second filter to cancel channel reflections, and a third filter to at least reduce noise. The DSP device is a receiver DSP of the SERDES.

A blind channel equalizer device for a radiofrequency receiver suitable for modulating the constant envelope signal of the transmission includes: an adjustable linear digital filter, defined at a point in time by the coefficients) thereof, able to filter an input signal in order to produce an output signal; an estimator able to estimate a power of the input signal; an adapter able to adapt the filter by calculating the coefficients of the filter at a point in time by subtracting, from the filter coefficients at a preceding point in time, the gradient of a cost function assigned with a correction coefficient. The cost function includes a first distance criterion between the square of the output signal and the power, wherein the correction coefficient is a product including a constant convergence coefficient and a scaling coefficient inversely proportional to the square of the power. Also disclosed is a related Radiofrequency receiver.

A reception device includes an equalization processing unit including a linear filter unit and a nonlinear filter unit and performing equalization process on a reception signal; a linear propagation channel estimation unit making propagation channel estimation using a known signal included in a reception signal to calculate a filter coefficient of the linear filter unit; and a synchronization processing unit performing synchronization process of correcting frequency deviation based on a signal output by the equalization processing unit, and when a predetermined condition is satisfied after executing first equalization process of outputting a reception signal filtered by the linear filter unit to the synchronization processing unit, the equalization processing unit starts second equalization process that is an adaptive equalization process of outputting a result of addition of a reception signal filtered by the linear filter unit and a reception signal filtered by the nonlinear filter unit to the synchronization processing unit.

The present invention is directed to communication method and techniques. In a specific embodiment, the present invention provides a receiver that interleaves data signal n-ways for n slices. Each of the n slices includes feedforward equalizer and decision feedback equalizers that are coupled to other slices. Each of the n slices also includes an analog-to-digital converter section that includes data and error slicers. There are other embodiments as well.

The present invention is directed to communication method and techniques. In a specific embodiment, the present invention provides a receiver that interleaves data signal n-ways for n slices. Each of the n slices includes feedforward equalizer and decision feedback equalizers that are coupled to other slices. Each of the n slices also includes an analog-to-digital converter section that includes data and error slicers. There are other embodiments as well.

The present invention is directed to communication method and techniques. In a specific embodiment, the present invention provides a receiver that interleaves data signal n-ways for n slices. Each of the n slices includes feedforward equalizer and decision feedback equalizers that are coupled to other slices. Each of the n slices also includes an analog-to-digital converter section that includes data and error slicers. There are other embodiments as well.

An RFID circuit and to a demodulator for an RFID circuit, the demodulator including an input and at least one output, a clock extractor connected to the input, a comparator connected to at least one output, a finite impulse response FIR filter arrangement connected to the input and connected to the comparator.

A data equalization system includes a data clock input configured to receive a clock signal. There is an input node operative to receive a data signal of transmission symbols that change state synchronously with the clock signal. There is a first tap coupled to the input node. A second tap is configured to receive a variation of the data signal. At least one of a weight of the first tap or a weight of the second tap is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol.