An attenuating device for a bus of a controller area network bus system based on differential voltage signals. The bus has first and second bus lines, having an attenuating circuit that provides a variable electrical resistance value between the first and second bus lines and that is operable in at least three circuit states. In a first circuit state, the first and second bus lines are connected via an attenuating resistor having a first resistance value. In a second circuit state, the first and second bus lines are connected via an attenuating resistor having a second resistance value. In a third circuit state, the first and second bus lines are connected via an attenuating resistor having a third resistance value. The first resistance value is lower than the second resistance value. The second resistance value is lower than the third resistance value.

A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

A communication system is configured to use a pulse width modulation signal as transmission code among a plurality of nodes connected to a communication line. A master node includes a transmission transistor connected to the communication line, a detector configured to detect a variation in current during the on-period of the transmission transistor, and a communication circuit configured to determine the off-timing of the transmission transistor based on the timing of occurrence of the variation in current (i.e., the on-timing of a second transmission transistor provided in a slave node). For example, the communication circuit can be configured to determine the off-timing of the transmission transistor such that the simultaneously-on period TB of the transmission transistor and the second transmission transistor fulfills TB=(2n−1)/2f, where f is the frequency of EMI noise.

A redriver chip includes a controller and a plurality of circuits coupled to the channel. The controller adjusts a set of parameters of the plurality of circuits to have first values during a first mode of operation and second values during a second mode of operation. The first values generate a first level of power consumption during the first mode of operation, and the second values generate a second level of power consumption during the second mode of operation. The first level of power consumption is lower than the second level of power consumption, and the first mode of operation corresponding to a low-power mode of the redriver chip.

A bus driving device includes at least three high-side output drivers and at least three low-side output drivers. A part of the high-side output drivers and a part of the low-side output drivers are alternately coupled in series, and the remains of the high-side output drivers and the low-side output drivers are alternately coupled in series. The part of the high-side output drivers and the part of the low-side output drivers receive an input digital signal and sequentially drive a first supply bus and a second supply bus based on the input digital signal, and the remains of the high-side output drivers and the low-side output drivers receive the inverted input digital signal and sequentially drive the first supply bus and the second supply bus based on the inverted input digital signal.

Various embodiments may employ neural networks at transmitting devices to compress transmit (TX) waveform distortion. In various embodiments, compressed TX waveform distortion information may be conveyed to a receiving device. In various embodiments, the signaling of TX waveform distortion information from a transmitting device to a receiving device may enable a receiving device to mitigate waveform distortion in a transmit waveform received from the transmitting device. Various embodiments include systems and methods of wireless communication by transmitting a waveform to a receiving device performed by a processor of a transmitting device. Various embodiments include systems and methods of wireless communication by receiving a waveform from a transmitting device performed by a processor of a receiving device.

A transmitter includes a pre-driver stage circuitry, a post-driver stage circuitry, and resistance adjustment circuits. The pre-driver stage circuitry is configured to output a second data signal according to a first data signal. The post-driver stage circuitry is configured to output a third data signal according to the second data signal. The resistance adjustment circuits are configured to provide a first variable resistor and a second variable resistor, and transmit a first power supply voltage and a second power supply voltage to at least one of the pre-driver stage circuitry or the post-driver stage circuitry, in order to adjust a slew rate of the third data signal.

This application provides a signal generation apparatus and method, and a system. The signal generation apparatus includes an encoder, a serializer, an equalizer, and N amplifiers. The encoder is configured to encode to-be-sent data, to obtain a first electrical signal. The serializer is configured to perform parallel-to-serial processing on the first electrical signal, to obtain a second electrical signal. The equalizer is configured to process the second electrical signal, to obtain a third electrical signal. The third electrical signal is amplified by the N amplifiers, to obtain N pairs of differential signals, where N is an integer greater than 2. In embodiments of this application, the N amplifiers amplify differential signals to obtain N pairs of differential signals, and the N pairs of differential signals are directly used as drive signals, so that power consumption for generating a drive signal can be reduced.

A bus driving device includes at least three high-side output drivers and at least three low-side output drivers. A part of the high-side output drivers and a part of the low-side output drivers are alternately coupled in series, and the remains of the high-side output drivers and the low-side output drivers are alternately coupled in series. The part of the high-side output drivers and the part of the low-side output drivers receive an input digital signal and sequentially drive a first supply bus and a second supply bus based on the input digital signal, and the remains of the high-side output drivers and the low-side output drivers receive the inverted input digital signal and sequentially drive the first supply bus and the second supply bus based on the inverted input digital signal.

A signal transmission circuit of a semiconductor device includes a first emphasis circuit and a second emphasis circuit. The first emphasis circuit feeds a signal of an output node back to an input node. The first emphasis circuit may perform a first emphasis operation on a signal of the input node and the signal of the output node by adjusting a feedback time of the first emphasis circuit. The second emphasis circuit may be connected in parallel with the first emphasis circuit to perform a feedback of the signal of the output node to the input node. The second emphasis circuit may perform a second emphasis operation on the signal of the input node and the signal of the output node by adjusting a feedback time of the second emphasis circuit.