An equalizer having a split folded cascode architecture includes a circuit having a differential pair with a single tail current source and split folded cascode branches. The single tail current source eliminates the input referred offset due to a mismatch in current sources. The folded cascode amplifier acts as the equalizer, which is split into a derivative path and a proportional path. The derivative path boosts the high frequency components of the received signal. The gain of the low frequency components of the received signal is adjusted by the proportional path. The derivative path includes variable capacitors and variable resistors which allow fixing a ‘zero’ frequency and peak gain frequency to a predetermined value, wherein frequencies greater than the ‘zero’ frequency are boosted. The proportional path includes variable resistors, which allow adjusting the low frequency gain without affecting the ‘zero’ frequency and peak gain frequency.

An equalizer having a split folded cascode architecture includes a circuit having a differential pair with a single tail current source and split folded cascode branches. The single tail current source eliminates the input referred offset due to a mismatch in current sources. The folded cascode amplifier acts as the equalizer, which is split into a derivative path and a proportional path. The derivative path boosts the high frequency components of the received signal. The gain of the low frequency components of the received signal is adjusted by the proportional path. The derivative path includes variable capacitors and variable resistors which allow fixing a ‘zero’ frequency and peak gain frequency to a predetermined value, wherein frequencies greater than the ‘zero’ frequency are boosted. The proportional path includes variable resistors, which allow adjusting the low frequency gain without affecting the ‘zero’ frequency and peak gain frequency.

A method and related apparatus for outputting an analog signal are disclosed. A plurality of transmit levels corresponding to respective predetermined equalization levels is provided. A stream of digital signals carrying data is provided. A transmit level from among the plurality of transmit levels based on the digital signals carrying data is selected. The selected transmit level is received, the selected transmit level is converted to an analog signal of the selected transmit level, and the analog signal of the selected transmit level is output over a signal interface.

A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

A transmitter of the present disclosure includes: an output terminal; a driver that performs transition of a voltage of the output terminal among a plurality of voltages; and a controller that controls the driver to cause transition start timing in one voltage transition in voltage transition among the plurality of voltages to be later than transition start timing in another voltage transition.

A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

A transmitter with low power and high accuracy equalization is shown. The transmitter includes a transmitter driver and a driver bias circuit. The transmitter driver receives data, and generates a positive differential output and a negative differential output to be transmitted by the transmitter. The driver bias circuit is coupled to the transmitter driver to bias the transmitter driver, wherein the driver bias circuit is configured to boost the bias level of the transmitter driver in response to transitions of the data.

A transmitter with low power and high accuracy equalization is shown. The transmitter includes a transmitter driver and a driver bias circuit. The transmitter driver receives data, and generates a positive differential output and a negative differential output to be transmitted by the transmitter. The driver bias circuit is coupled to the transmitter driver to bias the transmitter driver, wherein the driver bias circuit is configured to boost the bias level of the transmitter driver in response to transitions of the data.

A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

A system includes the transmitter that transmits a first adjustment signal obtained based on a first parameter, detects, based on an output potential of the transmitter, a second parameter that is among values settable to the first parameter and sets the second parameter and the receiver that receives the first adjustment signal from the transmitter and acquire a second adjustment signal by adjusting the first adjustment signal based on a third parameter, sets the third parameter, counts the number of errors of the second adjustment signal based on a difference between the second adjustment signal and the test pattern, determines, based on the number of errors of the second adjustment signal, the second parameter to be set in the transmitter and controls the connection of the terminal resistor to the input terminal based on the second parameter.