An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.

A transmitter of the present disclosure includes: an output terminal; a driver that performs transition of a voltage of the output terminal among a plurality of voltages; and a controller that controls the driver to cause transition start timing in one voltage transition in voltage transition among the plurality of voltages to be later than transition start timing in another voltage transition.

A transmitter of the present disclosure includes: an output terminal; a driver that performs transition of a voltage of the output terminal among a plurality of voltages; and a controller that controls the driver to cause transition start timing in one voltage transition in voltage transition among the plurality of voltages to be later than transition start timing in another voltage transition.

It is described a transmitter device (100) and a method for transmitting an analog signal (251, 261) via an electric cable (192). The transmitter device (100) comprises (a) a signal generation circuit (210) for generating a digital transmit signal (211) comprising a sequence of transmit symbols; (b) a filter circuit (230) for spectrally shaping the generated digital transmit signal (211, 221) and for outputting a filtered digital transmit signal (231); (c) a switching unit (240) comprising (c1) a first input terminal (242) for receiving the filtered digital transmit signal (231), (c2) a second input terminal (244) for receiving another digital transmit signal (297), (c3) an output terminal (246) for outputting a digital transmit output signal (241), wherein the digital transmit output signal (241) is based on, depending on a switching state of the switching unit (240), the filtered digital transmit signal (231) or the another digital transmit signal (297), and (c4) a control terminal (248) for receiving a control signal (285) from a control circuit (280), the control signal (285) being indicative for the switching state. The transmitter device (100) further comprises the control circuit (280); and a digital to analog converter (250) for receiving the digital transmit output signal (241) and for converting the received digital transmit output signal (241) to the analog signal (251, 261).

A system for compensating wire characteristics includes a transmission pre-emphasis module of a transmission transceiver that sends high level pre-emphasis training bits and low level pre-emphasis training bits along a wired connection, a reception pre-emphasis module of a receiver that receives the high level pre-emphasis training bits and low level pre-emphasis training bits along the wired connection, a pre-emphasis analysis module of the receiver that analyzes the high level pre-emphasis training bits and low level pre-emphasis training bits to determine a pre-emphasis level. The system further includes a controller that interfaces with the transmission transceiver and the receiver, the controller communicates the pre-emphasis level to the transmission transceiver.

A configurable transceiver includes a first transmitter, an edge rate controller, a second transmitter, a subtractor, a bandwidth controller and a main controller. The first transmitter is configured to generate a first signal for transmission via a transmission link. The second transmitter is configured to generate a replica signal associated with the first signal. The edge rate controller is communicatively coupled to the first and/or second transmitter and is configured to control an edge rate parameter of the first and/or second signal. The subtractor is configured to subtract the replica signal from a signal received via the transmission link. The bandwidth controller is configured to control a bandwidth parameter of a difference signal received from the output of the subtractor. The main controller chooses edge rate and bandwidth control words per desired link rates. It can also automatically find the maximum possible link speed.

A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.

The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes a waveform of a signal at the end of the signal line.

A transmitter of the present disclosure includes: an output terminal; a driver that performs transition of a voltage of the output terminal among a plurality of voltages; and a controller that controls the driver to cause transition start timing in one voltage transition in voltage transition among the plurality of voltages to be later than transition start timing in another voltage transition.

An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.