A radio receiver comprises a matched filter bank and a decision unit. The matched filter bank has a plurality of filter modules for generating correlation-strength data from a sampled radio signal, each filter module being configured to cross-correlate the sampled signal with data representing a respective filter sequence. The decision unit is configured to use the correlation-strength data to generate a sequence of decoded symbols from the sampled signal. The matched filter bank and/or decision unit are configured to determine the value of each symbol in the sequence in part based on the value of a respective earlier decoded symbol from the sequence of decoded symbols.

Filter characteristics of a first filter are improved while suppressing degradation in filter characteristics of a second filter. A multiplexer includes a first terminal, a second terminal, a first filter, a second filter, and a capacitive element. The first filter and the second filter are connected to an antenna via the first terminal. The first filter includes a plurality of series arm resonators, a plurality of parallel arm resonators, and an inductor. The inductor is provided between the parallel arm resonator and ground. A first end portion of the capacitive element is connected to a first path at a position in between the series arm resonator that is the closest to the first terminal and the second terminal. A second end portion of the capacitive element is connected between the parallel arm resonator and the inductor.

A radio receiver comprises a matched filter bank and a decision unit. The matched filter bank has a plurality of filter modules for generating correlation-strength data from a sampled radio signal, each filter module being configured to cross-correlate the sampled signal with data representing a respective filter sequence. The decision unit is configured to use the correlation-strength data to generate a sequence of decoded symbols from the sampled signal. The matched filter bank and/or decision unit are configured to determine the value of each symbol in the sequence in part based on the value of a respective earlier decoded symbol from the sequence of decoded symbols.

A BPSK demodulator circuit comprises: a sideband-separating and lower sideband signal-delaying unit which separates a modulated signal into a lower sideband and an upper sideband by a primary low pass filter and a primary high pass filter having a cut-off frequency as a carrier frequency, and which outputs an upper sideband analog signal and an analog signal delayed by ¼ of a cycle of the carrier frequency from a lower sideband analog signal; a data demodulating unit which demodulates digital data by means of latching, through a hysteresis circuit, an analog pulse signal appearing in accordance with the phase change part of a signal generated by the sum of the analog signals; and a data clock restoring unit which generates a data clock by using a data signal and a signal having the delayed lower sideband analog signal digitized through a comparator.

An interference cancellation (IC) processor, a method, a method of manufacturing a semiconductor device, and a method of constructing an integrated circuit are provided. The IC processor includes a plurality of mono interference cancellation (MIC) filter estimation processors; a combined effective channel calculation processor; a combined filter calculation processor; and a combined filter processor, including a first input connected to the output of the combined filter calculation processor, a second input for receiving a signal for setting a length of the combined filter that is connected to a second input of the IC processor, a third input connected to the input of the MIC-BRC processor, and an output for providing a filtered output of a de-rotated GMSK signal that is connected to a second output of the IC processor that provides a filtered output y.sub.i of the de-rotated GMSK signal.

The invention relates to a phase detection method (200), comprising the following steps: receiving a plurality of consecutive values of a receiving signal (Y) with a known sampling frequency f.sub.s as a reaction to a transmitting signal having a known transmitting frequency f.sub.w; determining two differential values (ΔY1, ΔY2), each coming from two consecutive values out of three consecutive values (Y1, Y2, Y3) of the receiving signal (Y); and determining a phase real part (U) and a phase imaginary part (V) of the receiving signal (Y) based on a linear relation between the phase real part (U), the phase imaginary part (V) and the two differential values (ΔY1, ΔY2).

Methods and systems for I/O mismatch calibration and compensation for wideband communication receivers may include receiving a radio frequency (RF) signal in a receiver of a communication device, down-sampling said received RF signal to generate a channel k and its image channel −k at baseband frequencies, determining average in-phase (I) and quadrature (Q) gain and phase mismatch of said channel k and said image channel −k, removing said average I and Q gain and phase mismatch of said channel k and said image channel −k, determining, after said removing said average I and Q gain and phase mismatch, a residual phase tilt of said channel k and said image channel −k, and compensating for said determined residual phase tilt of said channel k and said image channel −k utilizing a phase tilt correction filter.

A digital radio receiver adapted to receive radio signals modulated using continuous phase frequency shift keying, CPFSK. The receiver comprises means for receiving a radio signal (2), a correlator (8) arranged to estimate a frequency offset between the carrier frequency of the received radio signal and a nominal carrier frequency, means for correcting said frequency offset (4) and outputting a frequency-corrected radio signal (6), and a matched filter bank, MFB, which comprises a plurality of filters (20,22), each of which corresponds to a different bit pattern, for determining a bit sequence (36) from the frequency-corrected radio signal (6).

A signal detection method that allows characterization of a modulated signal to be efficiently determined. The method comprises the steps of receiving a data signal, processing the data signal to determine its value squaring the value of the signal; filtering the squared signal value to remove DC content; evaluating the resulting signal to determine if a single sinusoidal value remains; and determining that the presence of a single sinusoidal value as the resulting signal from the squaring and filtering steps indicates that the received data signal is a phase-shift key signal or conversely that the absence of such after a given number of cycle of squaring and filtering indicates a different modulation technique is present in the signal.

An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit; a data demodulation unit; and a data clock restoration unit.