Improved network traffic flow processing techniques are described. In a network device providing multiple processing planes, each processing plane comprising multiple processing units, techniques are described that take advantage of flow affinity/locality principles such that the same processing component of a processing plane, which previously performed processing for a network flow, is used for performing subsequent processing for the same network flow. This enables faster processing of network traffic flows by the network device. In certain implementations, the techniques described herein can be implemented in a network virtualization device (NVD) that is configured to perform network virtualization functions.

Network infrastructure systems including asymmetric Distributed Broadcast Select Switches and Asymmetric Network Interface Controllers for implementation in asymmetric networks and more particularly in cluster networks are provided.

A network system for a data center is described in which a switch fabric may provide full mesh interconnectivity such that any servers may communicate packet data to any other of the servers using any of a number of parallel data paths. Moreover, according to the techniques described herein, edge-positioned access nodes, optical permutation devices and core switches of the switch fabric may be configured and arranged in a way such that the parallel data paths provide single L2/L3 hop, full mesh interconnections between any pairwise combination of the access nodes, even in massive data centers having tens of thousands of servers. The plurality of optical permutation devices permute communications across the optical ports based on wavelength so as to provide, in some cases, full-mesh optical connectivity between edge-facing ports and core-facing ports.

Some examples provide a method for automatic network assembly. The following instructions may be used to implement automatic network assembly in a modular infrastructure. Instructions to automatically connect a management port to a management network. Instructions to automatically connect link ports to form a scalable ring. Instructions to automatically connect each modular infrastructure management device to a bay management network port.

A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.

The technology disclosed herein enables an L3 network fabric including one or more spine switches having a leaf-spine topology to be self-expanded. In a particular embodiment, a method provides transferring one or more probe messages from each of the spine switches. The probe messages detect whether new computing nodes have been attached to the communication network. The method further provides receiving a reply to at least one of the probe messages. The reply identifies a new computing node that is not yet included in the L3 fabric. In response to the reply, the method provides confirming physical network interfaces of the spine switches indicate valid connections to one or more new leaf switches of the new computing node, using L3 discovery protocols to ensure the connections conform to the leaf-spine topology, and transferring probe packets between the spine switches and leaf switches, including the new leaf switches, of computing nodes connected thereto to confirm configuration of all connections between the spine switches and the leaf switches of the computing nodes. Moreover, the method provides configuring L3 protocols for routing communications exchanged with the new computing node.

Methods, systems, and computer programs are presented for a switching server. One switching server includes a server, a switch module coupled to the server, and a switch controller coupled to the server and to the switch module. The server includes a processor executing an operating system that includes a network driver, and the network driver includes a first network device operating system (ndOS) program. Further, the switch module includes a switch fabric and input/output ports. The switch controller includes a processor and non-volatile storage, where the processor is configured to execute a second ndOS program. The first and second ndOS programs implement a global networking policy for a plurality of devices executing ndOS programs, the global networking policy including a definition for switching incoming packets through the plurality of devices executing the ndOS programs.

A method for line speed interconnect processing. The method includes receiving initial inputs from an input communications path, performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs, and performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs. The method further includes transmitting the resulting outputs out of the second stage at line speed.

An automated multi-fabric link aggregation system includes leaf switch devices that have leaf switch device downlink ports, that are included in a first network fabric, and that are aggregated to provide a first aggregation fabric. Each leaf switch device generates discovery communications including a first network fabric identifier for the first network fabric, and a first aggregation fabric identifier for the first aggregation fabric. The leaf switch devices then transmit the discovery communications via the leaf switch device downlink ports. I/O modules that have I/O module uplink port are included in a second network fabric and are aggregated to provide a second aggregation fabric. The I/O modules receive the discovery communications via each of the I/O module uplink ports, determine that each received discovery communication includes the first network fabric identifier and the first aggregation fabric identifier and, in response, automatically configure the I/O module uplink ports in a LAG.

An information processing apparatus includes a memory; and a processor coupled to the memory and the processor configured to exclude a combination for satisfying a condition from multiple combinations each including a number of shifts of multiple switch layers in a fat-tree network using Latin square, create relay settings for multiple switches for performing communication through multiple communication paths corresponding to remain combinations except the combination excluded from the multiple combinations, and transmit correspondingly the created relay settings to the multiple switches.