An integrated circuit for a receiving link device includes a processing device to detect, using an equalizer of the receiving link device, that a receiver (RX) pre-cursor value is outside of a threshold value based on a target RX tap value. The processing device further generates, based on the detecting, a plurality of tap messages having a plurality of up or down commands to one of decrease or increase a corresponding transmitter (TX) pre-cursor value of a transmitting link device. The processing device further causes the plurality of tap messages to be provided to a local transmitter to be transmitted to the transmitting link device. The plurality of tap messages is to cause the transmitting link device to adjust the corresponding TX pre-cursor value.

In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

A timing recovery apparatus for signal reception in a data transmission system comprises an equalizer to equalize a received signal and a phase detector connected after the timing recovery equalizer that generates a clock tone from absolute values of the received signal after equalization.

Disclosed are a clock and data recovery circuit, method and apparatus. The circuit comprises a receiving module for receiving an analog signal; a first equalization module connected to the receiving module, the first equalization module comprising a first totalizer and a second totalizer; a first sampling module connected to an output end of the first totalizer, the first sampling module comprising a first edge sampler and a second edge sampler that are connected to the output end of the first totalizer, respectively; a second sampling module connected to an output end of the second totalizer; a data processing module connected to both the first sampling module and the second sampling module; a clock recovery module connected to the data processing module; and an output module connected to the clock recovery module. In the present application, by means of the manner, a phase can be adjusted using a bias voltage, thereby accurately recovering clock information.

A receiving link device includes a receiver (RX) to receive a data signal from a transmitting link device, the receiver including an equalizer to detect RX tap values and a processing device coupled to the receiver, the processing device to perform operations including: programming the receiver with information related to target RX tap values that are associated RX pre-cursors or RX post-cursors; detecting, using the equalizer, that an RX pre-cursor value is greater or less than a target RX tap value; generating, based on the detecting, a tap message including an up or a down command to decrease or increase a corresponding transmitter (TX) pre-cursor value of the transmitting link device; and causing the tap message to be provided to a local transmitter to be transmitted to a remote receiver of the transmitting link device, which causes the transmitting link device to adjust the corresponding TX pre-cursor value.

A receiving link device includes a receiver (RX) to receive a data signal from a transmitting link device, the receiver including an equalizer to detect RX tap values and a processing device coupled to the receiver, the processing device to perform operations including: programming the receiver with information related to target RX tap values that are associated RX pre-cursors or RX post-cursors; detecting, using the equalizer, that an RX pre-cursor value is greater or less than a target RX tap value; generating, based on the detecting, a tap message including an up or a down command to decrease or increase a corresponding transmitter (TX) pre-cursor value of the transmitting link device; and causing the tap message to be provided to a local transmitter to be transmitted to a remote receiver of the transmitting link device, which causes the transmitting link device to adjust the corresponding TX pre-cursor value.

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.

Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.