An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit; a data demodulation unit; and a data clock restoration unit.

A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.

Systems and methods for blind detection of a numerology of a received signal are described. In one aspect, a method is provided for a user equipment (UE) to blindly detect the numerology of a received signal. The method includes correlating cyclic prefix (CP) signals in the received signal in the time domain based on a plurality of hypotheses of subcarrier spacing (SCS) and determining a numerology of the received signal for a corresponding hypothesis of SCS of the plurality of hypotheses based on the correlated CP signals.

A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

A circuit includes a serializer module that includes an input stage that samples an input signal to capture an edge location for each of the input signal in a given time frame. An edge encoder encodes the edge location for the input signal into a packet frame to specify where the edge location occurs in the given time frame for the input signal. A transmitter receives the packet frame from the edge decoder and converts the packet frame into a serial data stream. The transmitter communicates the edge location for the input signal via the serial data stream.

A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

Various examples are provided for jamming avoidance response (JAR), and photonic implementations thereof. In one example, a method includes generating optical pulses that correspond to raising envelope of a beat signal associated with an interference signal and a reference signal; generating optical spikes that correspond to positive zero crossing points of the reference signal; and providing a phase output that indicates whether the beat signal is leading or lagging the reference signal, the phase output based at least in part upon the optical spikes. An adjustment to a reference frequency can be determined based at least in part upon the optical pulses and the phase output. In another example, a JAR system includes photonic circuitry to generate the optical pulses; photonic circuitry to generate the optical spikes; and photonic circuitry to provide the phase output. A logic unit can determine the adjustment to the reference frequency.

An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit; a data demodulation unit; and a data clock restoration unit.

A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.