A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

An apparatus and a method for recovering clock and data from a multilevel pulse amplitude modulated signal received as input signal is suggested. The apparatus comprises a phase detector, a low-pass filter, a voltage-controlled oscillator, and a feedback loop forming a CDR loop. The voltage-controlled oscillator outputs a clock signal that is provided to the phase detector. The phase detector receives an MSB signal from a sampler. The apparatus also comprises an interleave circuit configured to receive the input signal and to generate two output signals having a smaller symbol rate than the input signal. The apparatus further comprises a logical gate configured to receive the output signals from the interleave circuit and to generate an enable signal for the phase detector indicating symmetrical transitions in the input signal. Lastly, the apparatus comprises a converter converting the output signals from the interleave circuit into an MSB and an LSB bit stream.

Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.

In one example, an apparatus includes an offset tunable edge slicer having an input to receive a pulse amplitude modulation signal. The offset tunable edge slicer also has a plurality of possible offset settings corresponding to a plurality of different reference voltages of the offset tunable edge slicer. A multiplexer has an output coupled to the input of the offset tunable edge slicer and an input to receive a control signal that selects one of the plurality of possible offset settings for the offset tunable edge slicer. A phase detector has an input coupled to an output of the offset tunable edge slicer.

A system for synthetically sampling an input signal to provide a sampled signal includes a sample clock and a mixer. The sample clock is configured to generate a sampling signal having a sampling frequency. The mixer is configured to receive the sampling signal and the input signal, and to output an intermediate frequency (IF) signal by mixing the sampling signal and the input signal. An offset voltage is introduced into the mixer with the sampling signal to provide a baseband image, the offset voltage being adjusted so that the baseband image of the IF signal has the same magnitude as a first harmonic image of the IF signal.

A parallel-serial conversion circuit including a data transmission unit to output first data and second data of a prescribed pattern in accordance with a second clock obtained by dividing a first clock, a first flip flop to receive the first data so as to output the first data in accordance with the first clock, a second flip flop to receive the second data so as to output the second data in accordance with the first clock, a selector to select one of the first data and the second data so as to output the selected data in accordance with the first clock, and an adjustment unit to compare the second data to be received by the second flip flop and the first data output from the first flip flop so as to adjust, based on a comparison result, a timing for the first flip flop to receive the first data.

A phase locked loop has an integer phase detector to detect an integer phase by measuring a cycle number, a fractional phase detector to detect a fractional phase of smaller than one cycle between a reference signal and the oscillation signal, a frequency error generator to generate a frequency error signal between the reference signal and the oscillation signal, a glitch corrector to correct the frequency error signal to generate and output a glitch-corrected signal and the frequency error signal, a phase error generator to generate a phase error by integrating an output signal of the glitch corrector, an oscillator controller to control an oscillation frequency of the oscillation signal, and a synchronous detector to detect whether a phase of the reference signal and a phase of the oscillation signal are in an phase-lock state, and to stop detection of the integer phase when the phase-lock state is detected.

A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.

In one embodiment, a local clock is synchronized to a master clock using a Kalman filter to determine state variables using a state transition matrix that includes at least one coefficient that is associated with a digital-to-analog converter (DAC), where the state variables include a unit step variable indicative of a unit step for the system. The local clock is controlled based on the state variables determined using the Kalman filter. The unit step is indicative of an amount by which the frequency of the local clock signal changes in response to a change in the digital input of the DAC.

The present disclosure relates to an adaptation method for data level (dLev) or data swing detection in a high-speed link system for multi-level (e.g. PAM-4) signaling. Provided are a receiver and a receiving method in which when a swing range of data received as an input is changed according to a channel condition, reference levels of data/swing detection samplers are not adaptively controlled, but the reference levels are fixed and a variable gain amplifier (VGA) is adaptively controlled for response to the change. Through the present disclosure, offset calibration of the data/swing detection samplers is more accurately performed and lower bit error rate (BER) is thus achieved.