A wireless transmission method and a transceiver for wireless transmission are disclosed. According to this method, information to be transmitted and transmission control information are encoded into packet length information of wireless frames for transmission, wherein the transmission control information is filled into synchronization packets, sequence number packets and data packets, and the information to be transmitted is only filled into the data packets. Specifically, the method includes sequentially polling data for transmission in units of transmission sequences, and longitudinally encoding the information to be transmitted and data check information into the data packets. The transmission sequences are separated and sorted by the synchronization packets and the sequence number packets, and the data packets are sorted by sequence number fields in the transmission sequence.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

A data reception device comprises: a first data input for receiving a first data signal and a clock input for receiving a clock signal; and a stability detection circuit adapted to generate: a first error signal indicating when a data transition of the first data signal occurs during a first period at least partially before a first significant clock edge of the clock signal; and a second error signal indicating when a data transition of the first data signal occurs during a second period at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal for adjusting the sampling time of the first data signal based on said first and second error signals.

A transceiver includes a transmitter which transmits clock-embedded data through a line, where the clock-embedded data includes a clock training pattern, a start pattern, an encoded payload, and an end pattern, and a receiver which receives the clock-embedded data through the line, detects a clock embedding-related error from the clock-embedded data, and outputs an error flag corresponding to the clock embedding-related error to the transmitter.

In one embodiment, a method receives a first time from a network device. The first time is derived from a first timing source in a first domain. The method receives a second time in a second domain from a second timing source. A difference time value is calculated between the first time and the second time. The method then sends the difference time value to the network device where the network device uses the difference time value to send a delay value to other computing devices to synchronize timing of the other computing devices in the second domain. The other computing devices are configured to synchronize the respective time using the delay value with mobile network devices to allow timing synchronization between the mobile network devices.

A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.

Disclosed in embodiments of this disclosure are a check code processing method, an electronic device and a storage medium. The check code processing method comprising: performing operations on m bits of the n.sup.th byte of a code block to obtain the n.sup.th bit of a first sequence; and performing operation on the first sequence of the code block with a same transmission period to obtain a check code.

A control method for an optical transceiver includes interrupting internal repetitive internal processing in response to a command from a host apparatus and executing an interrupt process for transmitting monitoring data. The method sets a processing mode of the interrupt process to a first processing mode when a processing time necessary to execute the interrupt process and one cycle of the repetitive processing is shorter than a threshold value, and to a second processing mode when the processing time necessary to execute the interrupt process and one cycle of the repetitive processing is longer than the threshold value. In the first mode, the interrupt process stores first monitoring data read out from a memory unit in a transmission register, stops the stretching of a clock signal, and subsequently reads out second monitoring data from the memory unit to follow the first monitoring data. In the second mode, the interrupt process stores the first monitoring data read out from the memory unit in the transmission register, reads out the second monitoring data from the memory unit, and subsequently stops the stretching of the clock signal.

In one implementation, a receiver has a module to calculate the cross-correlation between a portion of a digital representation of a received signal and a reference signal. The receiver also has a module to generate an estimate of a portion of a message potentially included in the digital representation of the received signal and a screening module to determine the likelihood that the received signal includes a message. For a received signal that is determined likely to include a message, the receiver includes a carrier refinement module to shift the frequency of carrier pulses in the digital representation of the received signal toward a desired frequency and to align the phase of carrier pulses in the digital representation of the received signal with a desired phase and a coherent matched filter to recover the message from the digital representation of the received signal.

A method of frequency search and error correction of clock and data recovery circuit, comprising: initializing a frequency search algorithm parameter; processing a frequency error parameter UP/DN signals according to the set algorithm parameter and starting the frequency search, in which, the algorithm accordingly counts the UP/DN signals. When a phase error signal transition occurs, a transition parameter JUMP is accumulated by 1, and an accumulation parameter SUM is obtained and is further judged that whether a frequency search result is to be output. Number of repeating times of verification and threshold parameters are set, accordingly a reset DCRL value is obtained to verifies a frequency locking result and outputs the result. The present invention improves accuracy of UP/DN pulse counting, increases stability and reliability of the frequency locking, avoids a false locking in the frequency locking, and prevents an excessive locking time in the frequency locking, overcomes error judgment of the frequency search caused by a random jitter, and correctly completes the frequency search and locking, avoids failure of the CDR caused by an error frequency locking.