Patent classifications
H04L7/08
Synchronization mechanism for high speed sensor interface
A sensor may determine a sampling pattern based on a group of synchronization signals received by the sensor. The sampling pattern may identify an expected time for receiving an upcoming synchronization signal. The sensor may trigger, based on the sampling pattern, a performance of a sensor operation associated with the upcoming synchronization signal. The performance of the sensor operation may be triggered before the upcoming synchronization signal is received.
METHOD AND APPARATUS FOR TIME SYNCHRONISATION IN WIRELESS NETWORKS
A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is configured for receiving and decoding a timestamp in a beacon frame transmitted repeatedly from the access point. This is used to control the output signal of a station physical layer clock (12) which is then used as a clock source for an application layer time synchronisation protocol. This application layer time synchronisation protocol can then be used in the station to control an operating system clock (8) for regulating playback of media.
METHOD AND APPARATUS FOR TIME SYNCHRONISATION IN WIRELESS NETWORKS
A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is configured for receiving and decoding a timestamp in a beacon frame transmitted repeatedly from the access point. This is used to control the output signal of a station physical layer clock (12) which is then used as a clock source for an application layer time synchronisation protocol. This application layer time synchronisation protocol can then be used in the station to control an operating system clock (8) for regulating playback of media.
Codeword Synchronization Method, Receiver, Network Device, and Network System
A codeword synchronization method includes determining a candidate in a plurality of bits of a data sequence received by a receive end, and determining a synchronization position based on the candidate bit, where the synchronization position indicates a start position of a codeword in the data sequence.
Codeword Synchronization Method, Receiver, Network Device, and Network System
A codeword synchronization method includes determining a candidate in a plurality of bits of a data sequence received by a receive end, and determining a synchronization position based on the candidate bit, where the synchronization position indicates a start position of a codeword in the data sequence.
Device and method for monitoring a sensor clock signal
A method monitors a sensor clock signal in a sensor unit, which is generated and output for a data transfer between the sensor unit and a control unit with a predefined period duration. A reference clock signal having a predefined reference period duration is received. The sensor clock signal is compared to the reference clock signal. Based on the comparison, a deviation of the current period duration of the sensor clock signal from a target period duration is detected. Based on the detected deviation, a counting pulse or a reset pulse is emitted.
Device and method for monitoring a sensor clock signal
A method monitors a sensor clock signal in a sensor unit, which is generated and output for a data transfer between the sensor unit and a control unit with a predefined period duration. A reference clock signal having a predefined reference period duration is received. The sensor clock signal is compared to the reference clock signal. Based on the comparison, a deviation of the current period duration of the sensor clock signal from a target period duration is detected. Based on the detected deviation, a counting pulse or a reset pulse is emitted.
INTERLEAVED SUB-SAMPLING PHASED ARRAY RECEIVER
A phased array may include a clock stage configured to generate shifted clock signals. Each shifted clock signal may include a different phase. The phased array may also include a beamforming stage configured to generate a beamformed signal that includes a beam formed in a direction based on summed signals. In addition, the phased array may include slices. Each slice may include a filter stage and a feedback stage. The filter stage may be configured to generate a corresponding summed signal by filtering a portion of blocker and noise interference in a corresponding receive signal based on blocking signals and the shifted clock signals. The feedback stage may be configured to generate the blocking signals based on the shifted clock signals and the corresponding summed signal. The blocking signals may be representative of the blocker and noise interference in the corresponding receive signal.
INTERLEAVED SUB-SAMPLING PHASED ARRAY RECEIVER
A phased array may include a clock stage configured to generate shifted clock signals. Each shifted clock signal may include a different phase. The phased array may also include a beamforming stage configured to generate a beamformed signal that includes a beam formed in a direction based on summed signals. In addition, the phased array may include slices. Each slice may include a filter stage and a feedback stage. The filter stage may be configured to generate a corresponding summed signal by filtering a portion of blocker and noise interference in a corresponding receive signal based on blocking signals and the shifted clock signals. The feedback stage may be configured to generate the blocking signals based on the shifted clock signals and the corresponding summed signal. The blocking signals may be representative of the blocker and noise interference in the corresponding receive signal.
Mission critical communication link hub
A method for hub for interfacing between a wireless mission critical communication link (MCCL) and a wired MCCL. The hub includes a wired interface a providing a physical layer connectivity to the wired MCCL; a plurality of ports coupled to the wired interface; a wireless interface providing a physical layer connectivity to the wireless MCCL; and a processor; and a memory containing instructions that, when executed by the processing circuitry, configure the hub to: receive a signal from a primary device through the wireless MCCL; determine a wireless communication cycle of the primary device; determine a wired communication cycle of a secondary device, wherein the secondary device is connected via the wired MCCL; synchronize a start time of the wired communication cycle to a start of the wireless communication cycle; and send the received signal to the secondary device at the synchronized start time of the wired communication cycle.