H04L7/10

METHOD, A COMPUTER PROGRAM PRODUCT, AND A CARRIER FOR INDICATING ONE-WAY LATENCY IN A DATA NETWORK
20180006919 · 2018-01-04 ·

Disclosed herein is a method, a computer program product, and a carrier for indicating one-way latency in a data network (N) between a first node (A) and a second node (B), wherein the data network (N) lacks continuous clock synchronization, comprising: a pre-synchronisation step, a measuring step, a post-synchronisation step, an interpolation step, and generating a latency profile. The present invention also relates to a computer program product incorporating the method, a carrier comprising the computer program product, and a method for indicating server functionality based on the first aspect.

PREAMBLE CONFIGURING METHOD IN THE WIRELESS LAN SYSTEM, AND A METHOD FOR A FRAME SYNCHRONIZATION

A method of configuring a preamble of a downlink frame for synchronization in data frame transmission of a 60 GHz wireless local area network system, the method comprising arranging a short preamble having a plurality of repetitive S symbols, and an IS symbol, and arranging a long preamble having a long cyclic prefix (CP) and a plurality of L symbols for frame synchronization and symbol timing by performing auto-correlation according to the length of window of the auto-correlation.

PREAMBLE CONFIGURING METHOD IN THE WIRELESS LAN SYSTEM, AND A METHOD FOR A FRAME SYNCHRONIZATION

A method of configuring a preamble of a downlink frame for synchronization in data frame transmission of a 60 GHz wireless local area network system, the method comprising arranging a short preamble having a plurality of repetitive S symbols, and an IS symbol, and arranging a long preamble having a long cyclic prefix (CP) and a plurality of L symbols for frame synchronization and symbol timing by performing auto-correlation according to the length of window of the auto-correlation.

Efficient frequency detectors for clock and data recovery circuits
11711199 · 2023-07-25 · ·

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

WIRELESS COMMUNICATION SYSTEM, TRANSMISSION METHOD AND RECEPTION METHOD
20230238989 · 2023-07-27 ·

The present invention allows a gain control to be appropriately effected even when a frame including no preamble signal block is used for wireless communications. The following processes are effected in a transmission power control unit 106 of a transmission unit. Specifically, an automatic transmission gain control unit 201 multiplies a transmission signal by a gain value that is the difference between the power of a signal loop-backed from a power amplifier 109 and the power of the transmission signal. A fixed transmission gain multiplying unit 202 multiplies the transmission signal by a predetermined gain value or by the gain value used in the automatic transmission gain control unit 201 during the preceding frame. A selection unit 203 selects the transmission signal as gain-controlled by the automatic transmission gain control unit 201 in a case of a preamble signal block being included in the frame of the transmission signal and selects the transmission signal as gain-controlled by the fixed transmission gain multiplying unit 202 in a case of no preamble signal block being included in the frame of the transmission signal.

WIRELESS COMMUNICATION SYSTEM, TRANSMISSION METHOD AND RECEPTION METHOD
20230238989 · 2023-07-27 ·

The present invention allows a gain control to be appropriately effected even when a frame including no preamble signal block is used for wireless communications. The following processes are effected in a transmission power control unit 106 of a transmission unit. Specifically, an automatic transmission gain control unit 201 multiplies a transmission signal by a gain value that is the difference between the power of a signal loop-backed from a power amplifier 109 and the power of the transmission signal. A fixed transmission gain multiplying unit 202 multiplies the transmission signal by a predetermined gain value or by the gain value used in the automatic transmission gain control unit 201 during the preceding frame. A selection unit 203 selects the transmission signal as gain-controlled by the automatic transmission gain control unit 201 in a case of a preamble signal block being included in the frame of the transmission signal and selects the transmission signal as gain-controlled by the fixed transmission gain multiplying unit 202 in a case of no preamble signal block being included in the frame of the transmission signal.

Drift detection in timing signal forwarded from memory controller to memory device
11709525 · 2023-07-25 · ·

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

Drift detection in timing signal forwarded from memory controller to memory device
11709525 · 2023-07-25 · ·

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS
20230224101 · 2023-07-13 ·

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS
20230224101 · 2023-07-13 ·

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.