The disclosure concerns a test apparatus comprising a drum (100) configured such that ink drops (200) deposited on the surface of the drum form a printed marking (210) on the surface of the drum. The test apparatus further comprises an ink removal unit (300) configured to remove ink from the surface of the drum. The drum is at least partially transmissive of light and a light source (800) is disposed inside the drum to controllably illuminate the drum.

An image inspection apparatus includes a processor configured to: divide a read image obtained by reading a printed image and a reference image representing an original shape of the printed image into plural regions having the identical shape, respectively; set a movement direction of the region for each of the divided regions of the reference image according to a feature of the reference image in the region; and inspect a deviation between the read image and the reference image for each of corresponding regions of the read image and the reference image by moving the region of the reference image in the movement direction which is set for the region.

An image data frame is received from an external source. An error concealment operation is performed on the received image data frame in response to determining that a first frame size of the received image data frame is erroneous. The first frame size of the image data frame is determined to be erroneous based on at least one frame synchronization signal associated with the image data frame. An image processing operation is performed on the received image data frame on which the error concealment operation has been performed, thereby enabling an image processing module to perform the image processing operation without entering into a deadlock state and thereby prevent a host processor from having to execute hardware resets of deadlocked modules.

An information processing apparatus includes a control unit and an operation unit. The control unit is configured to generate image data for image display. The operation unit includes a display unit, and is configured to display a screen on the display unit based on the image data generated by the control unit and to accept user operation. The control unit executes first processing for identifying, based on a state of signal output from the operation unit, whether a malfunction has occurred in one of the control unit and the operation unit. The operation unit executes, independently of the first processing by the control unit, second processing for identifying, based on a state of signal output from the control unit, whether the malfunction has occurred in the control unit or in the operation unit.

An image data frame is received from an external source. An error concealment operation is performed on the received image data frame in response to determining that a first frame size of the received image data frame is erroneous. The first frame size of the image data frame is determined to be erroneous based on at least one frame synchronization signal associated with the image data frame. An image processing operation is performed on the received image data frame on which the error concealment operation has been performed, thereby enabling an image processing module to perform the image processing operation without entering into a deadlock state and thereby prevent a host processor from having to execute hardware resets of deadlocked modules.

An image data frame is received from an external source. An error concealment operation is performed on the received image data frame in response to determining that a first frame size of the received image data frame is erroneous. The first frame size of the image data frame is determined to be erroneous based on at least one frame synchronization signal associated with the image data frame. An image processing operation is performed on the received image data frame on which the error concealment operation has been performed, thereby enabling an image processing module to perform the image processing operation without entering into a deadlock state and thereby prevent a host processor from having to execute hardware resets of deadlocked modules.

An information processing apparatus includes a control unit and an operation unit. The control unit is configured to generate image data for image display. The operation unit includes a display unit, and is configured to display a screen on the display unit based on the image data generated by the control unit and to accept user operation. The control unit executes first processing for identifying, based on a state of signal output from the operation unit, whether a malfunction has occurred in one of the control unit and the operation unit. The operation unit executes, independently of the first processing by the control unit, second processing for identifying, based on a state of signal output from the control unit, whether the malfunction has occurred in the control unit or in the operation unit.

A signal processing board includes a six-layer substrate in which six wiring layers are stacked, and a first semiconductor element and a second semiconductor element mounted on the outer surface of a first layer of the six wiring layers. A plurality of signal transmission patterns are formed in the first layer, a third layer, a fourth layer, and a sixth layer of the six wiring layers. A first ground pattern is formed in a second layer. A second ground pattern is formed in a fifth layer. A first power supply pattern is formed in one of the fourth layer, the fifth layer, and the sixth layer. A second power supply pattern is formed in one of the fourth layer, the fifth layer, and the sixth layer.

A signal processing board includes a six-layer substrate in which six wiring layers are stacked, and a first semiconductor element and a second semiconductor element mounted on the outer surface of a first layer of the six wiring layers. A plurality of signal transmission patterns are formed in the first layer, a third layer, a fourth layer, and a sixth layer of the six wiring layers. A first ground pattern is formed in a second layer. A second ground pattern is formed in a fifth layer. A first power supply pattern is formed in one of the fourth layer, the fifth layer, and the sixth layer. A second power supply pattern is formed in one of the fourth layer, the fifth layer, and the sixth layer.

A hardware processor includes: a communication part connected to the hardware processor; a rasterization processing time predictor that predicts a rasterization processing time required for rasterization processing; an output setting information extractor that extracts output setting information from print information about each page and transmits the output setting information to the hardware processor; a warm-up start time calculator that calculates a warm-up start time at which the hardware processor starts warm-up processing in accordance with productivity information about the hardware processor; a warm-up start notifier that notifies the hardware processor of a start of the warm-up processing, when a current time reaches the warm-up start time; a rasterization processor that transmits image data to the hardware processor, the image data being generated by performing the rasterization processing for each page; and a print start notifier that notifies the hardware processor of a print start after the warm-up processing is completed.