A radiation detector includes control and data lines extending respectively in mutually-orthogonal first and second directions, photoelectric conversion parts respectively in regions defined by the control and data lines, noise detecting parts outside a region including the photoelectric conversion parts, a control circuit inputting control signals to first and second thin film transistors located respectively in the photoelectric conversion and noise detecting parts, a signal detection circuit reading image data and noise signals respectively from the photoelectric conversion and noise detecting parts, and an image configuration circuit configuring a radiation image based on the signals that are read. The signals from the photoelectric conversion parts adjacent to the noise detecting parts are not read and/or are not used by the image configuration circuit when configuring the radiation image, and/or the photoelectric conversion parts adjacent to the noise detecting parts are not electrically connected with the control and/or signal detection circuits.

An imaging pixel formed by a photodetector connected to a reading circuit comprising: an integration capacitance, a transistor for resetting the integration capacitance, a coupling transistor between the photodetector and the integration capacitance, a memorisation capacitance, a second transistor for resetting the memorisation capacitance, a memorisation switch between the integration capacitance and the memorisation capacitance, to enable different configurations corresponding to different phases of assessing parameters of the pixel and in particular a ratio R=Cint/Cmem.

An imaging pixel formed by a photodetector connected to a reading circuit comprising: an integration capacitance, a transistor for resetting the integration capacitance, a coupling transistor between the photodetector and the integration capacitance, a memorisation capacitance, a second transistor for resetting the memorisation capacitance, a memorisation switch between the integration capacitance and the memorisation capacitance, to enable different configurations corresponding to different phases of assessing parameters of the pixel and in particular a ratio R=Cint/Cmem.

In a solid-state imaging element equipped with per-column ADCs, noise is reduced. A test signal source generates a test signal of a predetermined level. An analog-to-digital converter increases/decreases an analog signal according to an analog gain selected from among a plurality of analog gains, and converts the increased/decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, either a test signal or a pixel signal to the analog-to-digital converter. A correction value calculation section obtains, on the basis of the test signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section corrects the digital signal according to the outputted correction value.

An image sensor includes a pixel array including a first pixel and a second pixel which are connected to a same column line, the first pixel including 2N sub-pixels sharing a first floating diffusion node and the second pixel including 2N sub-pixels sharing a second floating diffusion node, wherein N is a positive integer greater than or equal to two, a timing generator configured to change a reset order and a readout order of 4N sub-pixels included in the first pixel and the second pixel, according to an exposure time setting value, and output a row address according to the changed orders, and a row driver configured to drive the pixel array based on the row address.

An image sensor includes a pixel array including a first pixel and a second pixel which are connected to a same column line, the first pixel including 2N sub-pixels sharing a first floating diffusion node and the second pixel including 2N sub-pixels sharing a second floating diffusion node, wherein N is a positive integer greater than or equal to two, a timing generator configured to change a reset order and a readout order of 4N sub-pixels included in the first pixel and the second pixel, according to an exposure time setting value, and output a row address according to the changed orders, and a row driver configured to drive the pixel array based on the row address.

The dynamic range of a solid-state imaging element including a comparator is expanded.

The solid-state imaging element includes a pixel circuit and a comparison transistor. In the solid-state imaging element, the pixel circuit generates a pixel signal and outputs the pixel signal to a vertical signal line. Further, the comparison transistor has a source connected to a constant current source configured to supply a constant current to the vertical signal line. The comparison transistor has a gate to which a predetermined reference signal is input. Further, the comparison transistor has a drain from which a comparison result between the pixel signal and the reference signal is output.

An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.

An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.

A signal processing device according to the present technology includes a multistage-branching-wired-line unit that supplies the same signal to a plurality of target elements via multistage-branched wired lines, and a logic circuit arranged at each of stages of the multistage-branching-wired-line unit, in which the wired lines in at least a certain space between the stages in the multistage-branching-wired-line unit cross each other.